Browse Registers In Our Database

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Registers in Espressif Systems /ESP32-C3 /EXTMEM

  1. CACHE_ACS_CNT_CLR
  2. CACHE_ACS_CNT_CLR
  3. CACHE_CONF_MISC
  4. CACHE_CONF_MISC
  5. CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON
  6. CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON
  7. CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE
  8. CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE
  9. CACHE_ILG_INT_CLR
  10. CACHE_ILG_INT_CLR
  11. CACHE_ILG_INT_ENA
  12. CACHE_ILG_INT_ENA
  13. CACHE_ILG_INT_ST
  14. CACHE_ILG_INT_ST
  15. CACHE_MMU_FAULT_CONTENT
  16. CACHE_MMU_FAULT_CONTENT
  17. CACHE_MMU_FAULT_VADDR
  18. CACHE_MMU_FAULT_VADDR
  19. CACHE_MMU_OWNER
  20. CACHE_MMU_OWNER
  21. CACHE_MMU_POWER_CTRL
  22. CACHE_MMU_POWER_CTRL
  23. CACHE_PRELOAD_INT_CTRL
  24. CACHE_PRELOAD_INT_CTRL
  25. CACHE_REQUEST
  26. CACHE_REQUEST
  27. CACHE_STATE
  28. CACHE_STATE
  29. CACHE_SYNC_INT_CTRL
  30. CACHE_SYNC_INT_CTRL
  31. CACHE_WRAP_AROUND_CTRL
  32. CACHE_WRAP_AROUND_CTRL
  33. CLOCK_GATE
  34. CLOCK_GATE
  35. CORE0_ACS_CACHE_INT_CLR
  36. CORE0_ACS_CACHE_INT_CLR
  37. CORE0_ACS_CACHE_INT_ENA
  38. CORE0_ACS_CACHE_INT_ENA
  39. CORE0_ACS_CACHE_INT_ST
  40. CORE0_ACS_CACHE_INT_ST
  41. CORE0_DBUS_REJECT_ST
  42. CORE0_DBUS_REJECT_ST
  43. CORE0_DBUS_REJECT_VADDR
  44. CORE0_DBUS_REJECT_VADDR
  45. CORE0_IBUS_REJECT_ST
  46. CORE0_IBUS_REJECT_ST
  47. CORE0_IBUS_REJECT_VADDR
  48. CORE0_IBUS_REJECT_VADDR
  49. DBUS_ACS_CNT
  50. DBUS_ACS_CNT
  51. DBUS_ACS_FLASH_MISS_CNT
  52. DBUS_ACS_FLASH_MISS_CNT
  53. DBUS_PMS_TBL_ATTR
  54. DBUS_PMS_TBL_ATTR
  55. DBUS_PMS_TBL_BOUNDARY0
  56. DBUS_PMS_TBL_BOUNDARY0
  57. DBUS_PMS_TBL_BOUNDARY1
  58. DBUS_PMS_TBL_BOUNDARY1
  59. DBUS_PMS_TBL_BOUNDARY2
  60. DBUS_PMS_TBL_BOUNDARY2
  61. DBUS_PMS_TBL_LOCK
  62. DBUS_PMS_TBL_LOCK
  63. DBUS_TO_FLASH_END_VADDR
  64. DBUS_TO_FLASH_END_VADDR
  65. DBUS_TO_FLASH_START_VADDR
  66. DBUS_TO_FLASH_START_VADDR
  67. IBUS_ACS_CNT
  68. IBUS_ACS_CNT
  69. IBUS_ACS_MISS_CNT
  70. IBUS_ACS_MISS_CNT
  71. IBUS_PMS_TBL_ATTR
  72. IBUS_PMS_TBL_ATTR
  73. IBUS_PMS_TBL_BOUNDARY0
  74. IBUS_PMS_TBL_BOUNDARY0
  75. IBUS_PMS_TBL_BOUNDARY1
  76. IBUS_PMS_TBL_BOUNDARY1
  77. IBUS_PMS_TBL_BOUNDARY2
  78. IBUS_PMS_TBL_BOUNDARY2
  79. IBUS_PMS_TBL_LOCK
  80. IBUS_PMS_TBL_LOCK
  81. IBUS_TO_FLASH_END_VADDR
  82. IBUS_TO_FLASH_END_VADDR
  83. IBUS_TO_FLASH_START_VADDR
  84. IBUS_TO_FLASH_START_VADDR
  85. ICACHE_ATOMIC_OPERATE_ENA
  86. ICACHE_ATOMIC_OPERATE_ENA
  87. ICACHE_AUTOLOAD_CTRL
  88. ICACHE_AUTOLOAD_CTRL
  89. ICACHE_AUTOLOAD_SCT0_ADDR
  90. ICACHE_AUTOLOAD_SCT0_ADDR
  91. ICACHE_AUTOLOAD_SCT0_SIZE
  92. ICACHE_AUTOLOAD_SCT0_SIZE
  93. ICACHE_AUTOLOAD_SCT1_ADDR
  94. ICACHE_AUTOLOAD_SCT1_ADDR
  95. ICACHE_AUTOLOAD_SCT1_SIZE
  96. ICACHE_AUTOLOAD_SCT1_SIZE
  97. ICACHE_CTRL
  98. ICACHE_CTRL
  99. ICACHE_CTRL1
  100. ICACHE_CTRL1
  101. ICACHE_FREEZE
  102. ICACHE_FREEZE
  103. ICACHE_LOCK_ADDR
  104. ICACHE_LOCK_ADDR
  105. ICACHE_LOCK_CTRL
  106. ICACHE_LOCK_CTRL
  107. ICACHE_LOCK_SIZE
  108. ICACHE_LOCK_SIZE
  109. ICACHE_PRELOAD_ADDR
  110. ICACHE_PRELOAD_ADDR
  111. ICACHE_PRELOAD_CTRL
  112. ICACHE_PRELOAD_CTRL
  113. ICACHE_PRELOAD_SIZE
  114. ICACHE_PRELOAD_SIZE
  115. ICACHE_PRELOCK_CTRL
  116. ICACHE_PRELOCK_CTRL
  117. ICACHE_PRELOCK_SCT0_ADDR
  118. ICACHE_PRELOCK_SCT0_ADDR
  119. ICACHE_PRELOCK_SCT1_ADDR
  120. ICACHE_PRELOCK_SCT1_ADDR
  121. ICACHE_PRELOCK_SCT_SIZE
  122. ICACHE_PRELOCK_SCT_SIZE
  123. ICACHE_SYNC_ADDR
  124. ICACHE_SYNC_ADDR
  125. ICACHE_SYNC_CTRL
  126. ICACHE_SYNC_CTRL
  127. ICACHE_SYNC_SIZE
  128. ICACHE_SYNC_SIZE
  129. ICACHE_TAG_POWER_CTRL
  130. ICACHE_TAG_POWER_CTRL
  131. REG_DATE
  132. REG_DATE