Browse Registers In Our Database

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Registers in Espressif Systems /ESP32-C6 /EXTMEM

  1. CACHE_LOCK_ADDR
  2. CACHE_LOCK_ADDR
  3. CACHE_LOCK_CTRL
  4. CACHE_LOCK_CTRL
  5. CACHE_LOCK_MAP
  6. CACHE_LOCK_MAP
  7. CACHE_LOCK_SIZE
  8. CACHE_LOCK_SIZE
  9. CACHE_SYNC_ADDR
  10. CACHE_SYNC_ADDR
  11. CACHE_SYNC_CTRL
  12. CACHE_SYNC_CTRL
  13. CACHE_SYNC_MAP
  14. CACHE_SYNC_MAP
  15. CACHE_SYNC_SIZE
  16. CACHE_SYNC_SIZE
  17. CLOCK_GATE
  18. CLOCK_GATE
  19. DATE
  20. DATE
  21. L1_BUS0_ACS_CONFLICT_CNT
  22. L1_BUS0_ACS_CONFLICT_CNT
  23. L1_BUS0_ACS_HIT_CNT
  24. L1_BUS0_ACS_HIT_CNT
  25. L1_BUS0_ACS_MISS_CNT
  26. L1_BUS0_ACS_MISS_CNT
  27. L1_BUS0_ACS_NXTLVL_CNT
  28. L1_BUS0_ACS_NXTLVL_CNT
  29. L1_BUS1_ACS_CONFLICT_CNT
  30. L1_BUS1_ACS_CONFLICT_CNT
  31. L1_BUS1_ACS_HIT_CNT
  32. L1_BUS1_ACS_HIT_CNT
  33. L1_BUS1_ACS_MISS_CNT
  34. L1_BUS1_ACS_MISS_CNT
  35. L1_BUS1_ACS_NXTLVL_CNT
  36. L1_BUS1_ACS_NXTLVL_CNT
  37. L1_BYPASS_CACHE_CONF
  38. L1_BYPASS_CACHE_CONF
  39. L1_CACHE_ACS_CNT_CTRL
  40. L1_CACHE_ACS_CNT_CTRL
  41. L1_CACHE_ACS_CNT_INT_CLR
  42. L1_CACHE_ACS_CNT_INT_CLR
  43. L1_CACHE_ACS_CNT_INT_ENA
  44. L1_CACHE_ACS_CNT_INT_ENA
  45. L1_CACHE_ACS_CNT_INT_RAW
  46. L1_CACHE_ACS_CNT_INT_RAW
  47. L1_CACHE_ACS_CNT_INT_ST
  48. L1_CACHE_ACS_CNT_INT_ST
  49. L1_CACHE_ACS_FAIL_ID_ATTR
  50. L1_CACHE_ACS_FAIL_ID_ATTR
  51. L1_CACHE_ACS_FAIL_INT_CLR
  52. L1_CACHE_ACS_FAIL_INT_CLR
  53. L1_CACHE_ACS_FAIL_INT_ENA
  54. L1_CACHE_ACS_FAIL_INT_ENA
  55. L1_CACHE_ACS_FAIL_INT_RAW
  56. L1_CACHE_ACS_FAIL_INT_RAW
  57. L1_CACHE_ACS_FAIL_INT_ST
  58. L1_CACHE_ACS_FAIL_INT_ST
  59. L1_CACHE_ATOMIC_CONF
  60. L1_CACHE_ATOMIC_CONF
  61. L1_CACHE_AUTOLOAD_BUF_CLR_CTRL
  62. L1_CACHE_AUTOLOAD_BUF_CLR_CTRL
  63. L1_CACHE_AUTOLOAD_CTRL
  64. L1_CACHE_AUTOLOAD_CTRL
  65. L1_CACHE_AUTOLOAD_SCT0_ADDR
  66. L1_CACHE_AUTOLOAD_SCT0_ADDR
  67. L1_CACHE_AUTOLOAD_SCT0_SIZE
  68. L1_CACHE_AUTOLOAD_SCT0_SIZE
  69. L1_CACHE_AUTOLOAD_SCT1_ADDR
  70. L1_CACHE_AUTOLOAD_SCT1_ADDR
  71. L1_CACHE_AUTOLOAD_SCT1_SIZE
  72. L1_CACHE_AUTOLOAD_SCT1_SIZE
  73. L1_CACHE_AUTOLOAD_SCT2_ADDR
  74. L1_CACHE_AUTOLOAD_SCT2_ADDR
  75. L1_CACHE_AUTOLOAD_SCT2_SIZE
  76. L1_CACHE_AUTOLOAD_SCT2_SIZE
  77. L1_CACHE_AUTOLOAD_SCT3_ADDR
  78. L1_CACHE_AUTOLOAD_SCT3_ADDR
  79. L1_CACHE_AUTOLOAD_SCT3_SIZE
  80. L1_CACHE_AUTOLOAD_SCT3_SIZE
  81. L1_CACHE_BLOCKSIZE_CONF
  82. L1_CACHE_BLOCKSIZE_CONF
  83. L1_CACHE_CACHESIZE_CONF
  84. L1_CACHE_CACHESIZE_CONF
  85. L1_CACHE_CTRL
  86. L1_CACHE_CTRL
  87. L1_CACHE_DATA_MEM_ACS_CONF
  88. L1_CACHE_DATA_MEM_ACS_CONF
  89. L1_CACHE_DATA_MEM_POWER_CTRL
  90. L1_CACHE_DATA_MEM_POWER_CTRL
  91. L1_CACHE_DEBUG_BUS
  92. L1_CACHE_DEBUG_BUS
  93. L1_CACHE_FREEZE_CTRL
  94. L1_CACHE_FREEZE_CTRL
  95. L1_CACHE_OBJECT_CTRL
  96. L1_CACHE_OBJECT_CTRL
  97. L1_CACHE_PRELOAD_CTRL
  98. L1_CACHE_PRELOAD_CTRL
  99. L1_CACHE_PRELOAD_RST_CTRL
  100. L1_CACHE_PRELOAD_RST_CTRL
  101. L1_CACHE_PRELOCK_CONF
  102. L1_CACHE_PRELOCK_CONF
  103. L1_CACHE_PRELOCK_SCT0_ADDR
  104. L1_CACHE_PRELOCK_SCT0_ADDR
  105. L1_CACHE_SYNC_PRELOAD_EXCEPTION
  106. L1_CACHE_SYNC_PRELOAD_EXCEPTION
  107. L1_CACHE_SYNC_PRELOAD_INT_CLR
  108. L1_CACHE_SYNC_PRELOAD_INT_CLR
  109. L1_CACHE_SYNC_PRELOAD_INT_ENA
  110. L1_CACHE_SYNC_PRELOAD_INT_ENA
  111. L1_CACHE_SYNC_PRELOAD_INT_RAW
  112. L1_CACHE_SYNC_PRELOAD_INT_RAW
  113. L1_CACHE_SYNC_PRELOAD_INT_ST
  114. L1_CACHE_SYNC_PRELOAD_INT_ST
  115. L1_CACHE_SYNC_RST_CTRL
  116. L1_CACHE_SYNC_RST_CTRL
  117. L1_CACHE_TAG_MEM_ACS_CONF
  118. L1_CACHE_TAG_MEM_ACS_CONF
  119. L1_CACHE_TAG_MEM_POWER_CTRL
  120. L1_CACHE_TAG_MEM_POWER_CTRL
  121. L1_CACHE_VADDR
  122. L1_CACHE_VADDR
  123. L1_CACHE_WAY_OBJECT
  124. L1_CACHE_WAY_OBJECT
  125. L1_CACHE_WRAP_AROUND_CTRL
  126. L1_CACHE_WRAP_AROUND_CTRL
  127. L1_DBUS2_ACS_CONFLICT_CNT
  128. L1_DBUS2_ACS_CONFLICT_CNT
  129. L1_DBUS2_ACS_HIT_CNT
  130. L1_DBUS2_ACS_HIT_CNT
  131. L1_DBUS2_ACS_MISS_CNT
  132. L1_DBUS2_ACS_MISS_CNT
  133. L1_DBUS2_ACS_NXTLVL_CNT
  134. L1_DBUS2_ACS_NXTLVL_CNT
  135. L1_DBUS3_ACS_CONFLICT_CNT
  136. L1_DBUS3_ACS_CONFLICT_CNT
  137. L1_DBUS3_ACS_HIT_CNT
  138. L1_DBUS3_ACS_HIT_CNT
  139. L1_DBUS3_ACS_MISS_CNT
  140. L1_DBUS3_ACS_MISS_CNT
  141. L1_DBUS3_ACS_NXTLVL_CNT
  142. L1_DBUS3_ACS_NXTLVL_CNT
  143. L1_DCACHE_ACS_FAIL_ADDR
  144. L1_DCACHE_ACS_FAIL_ADDR
  145. L1_DCACHE_PRELOAD_ADDR
  146. L1_DCACHE_PRELOAD_ADDR
  147. L1_DCACHE_PRELOAD_SIZE
  148. L1_DCACHE_PRELOAD_SIZE
  149. L1_DCACHE_PRELOCK_SCT1_ADDR
  150. L1_DCACHE_PRELOCK_SCT1_ADDR
  151. L1_DCACHE_PRELOCK_SCT_SIZE
  152. L1_DCACHE_PRELOCK_SCT_SIZE
  153. L1_IBUS0_ACS_CONFLICT_CNT
  154. L1_IBUS0_ACS_CONFLICT_CNT
  155. L1_IBUS0_ACS_HIT_CNT
  156. L1_IBUS0_ACS_HIT_CNT
  157. L1_IBUS0_ACS_MISS_CNT
  158. L1_IBUS0_ACS_MISS_CNT
  159. L1_IBUS0_ACS_NXTLVL_CNT
  160. L1_IBUS0_ACS_NXTLVL_CNT
  161. L1_IBUS1_ACS_CONFLICT_CNT
  162. L1_IBUS1_ACS_CONFLICT_CNT
  163. L1_IBUS1_ACS_HIT_CNT
  164. L1_IBUS1_ACS_HIT_CNT
  165. L1_IBUS1_ACS_MISS_CNT
  166. L1_IBUS1_ACS_MISS_CNT
  167. L1_IBUS1_ACS_NXTLVL_CNT
  168. L1_IBUS1_ACS_NXTLVL_CNT
  169. L1_IBUS2_ACS_CONFLICT_CNT
  170. L1_IBUS2_ACS_CONFLICT_CNT
  171. L1_IBUS2_ACS_HIT_CNT
  172. L1_IBUS2_ACS_HIT_CNT
  173. L1_IBUS2_ACS_MISS_CNT
  174. L1_IBUS2_ACS_MISS_CNT
  175. L1_IBUS2_ACS_NXTLVL_CNT
  176. L1_IBUS2_ACS_NXTLVL_CNT
  177. L1_IBUS3_ACS_CONFLICT_CNT
  178. L1_IBUS3_ACS_CONFLICT_CNT
  179. L1_IBUS3_ACS_HIT_CNT
  180. L1_IBUS3_ACS_HIT_CNT
  181. L1_IBUS3_ACS_MISS_CNT
  182. L1_IBUS3_ACS_MISS_CNT
  183. L1_IBUS3_ACS_NXTLVL_CNT
  184. L1_IBUS3_ACS_NXTLVL_CNT
  185. L1_ICACHE0_ACS_FAIL_ADDR
  186. L1_ICACHE0_ACS_FAIL_ADDR
  187. L1_ICACHE0_ACS_FAIL_ID_ATTR
  188. L1_ICACHE0_ACS_FAIL_ID_ATTR
  189. L1_ICACHE0_AUTOLOAD_CTRL
  190. L1_ICACHE0_AUTOLOAD_CTRL
  191. L1_ICACHE0_AUTOLOAD_SCT0_ADDR
  192. L1_ICACHE0_AUTOLOAD_SCT0_ADDR
  193. L1_ICACHE0_AUTOLOAD_SCT0_SIZE
  194. L1_ICACHE0_AUTOLOAD_SCT0_SIZE
  195. L1_ICACHE0_AUTOLOAD_SCT1_ADDR
  196. L1_ICACHE0_AUTOLOAD_SCT1_ADDR
  197. L1_ICACHE0_AUTOLOAD_SCT1_SIZE
  198. L1_ICACHE0_AUTOLOAD_SCT1_SIZE
  199. L1_ICACHE0_PRELOAD_ADDR
  200. L1_ICACHE0_PRELOAD_ADDR
  201. L1_ICACHE0_PRELOAD_CTRL
  202. L1_ICACHE0_PRELOAD_CTRL
  203. L1_ICACHE0_PRELOAD_SIZE
  204. L1_ICACHE0_PRELOAD_SIZE
  205. L1_ICACHE0_PRELOCK_CONF
  206. L1_ICACHE0_PRELOCK_CONF
  207. L1_ICACHE0_PRELOCK_SCT0_ADDR
  208. L1_ICACHE0_PRELOCK_SCT0_ADDR
  209. L1_ICACHE0_PRELOCK_SCT1_ADDR
  210. L1_ICACHE0_PRELOCK_SCT1_ADDR
  211. L1_ICACHE0_PRELOCK_SCT_SIZE
  212. L1_ICACHE0_PRELOCK_SCT_SIZE
  213. L1_ICACHE1_ACS_FAIL_ADDR
  214. L1_ICACHE1_ACS_FAIL_ADDR
  215. L1_ICACHE1_ACS_FAIL_ID_ATTR
  216. L1_ICACHE1_ACS_FAIL_ID_ATTR
  217. L1_ICACHE1_AUTOLOAD_CTRL
  218. L1_ICACHE1_AUTOLOAD_CTRL
  219. L1_ICACHE1_AUTOLOAD_SCT0_ADDR
  220. L1_ICACHE1_AUTOLOAD_SCT0_ADDR
  221. L1_ICACHE1_AUTOLOAD_SCT0_SIZE
  222. L1_ICACHE1_AUTOLOAD_SCT0_SIZE
  223. L1_ICACHE1_AUTOLOAD_SCT1_ADDR
  224. L1_ICACHE1_AUTOLOAD_SCT1_ADDR
  225. L1_ICACHE1_AUTOLOAD_SCT1_SIZE
  226. L1_ICACHE1_AUTOLOAD_SCT1_SIZE
  227. L1_ICACHE1_PRELOAD_ADDR
  228. L1_ICACHE1_PRELOAD_ADDR
  229. L1_ICACHE1_PRELOAD_CTRL
  230. L1_ICACHE1_PRELOAD_CTRL
  231. L1_ICACHE1_PRELOAD_SIZE
  232. L1_ICACHE1_PRELOAD_SIZE
  233. L1_ICACHE1_PRELOCK_CONF
  234. L1_ICACHE1_PRELOCK_CONF
  235. L1_ICACHE1_PRELOCK_SCT0_ADDR
  236. L1_ICACHE1_PRELOCK_SCT0_ADDR
  237. L1_ICACHE1_PRELOCK_SCT1_ADDR
  238. L1_ICACHE1_PRELOCK_SCT1_ADDR
  239. L1_ICACHE1_PRELOCK_SCT_SIZE
  240. L1_ICACHE1_PRELOCK_SCT_SIZE
  241. L1_ICACHE2_ACS_FAIL_ADDR
  242. L1_ICACHE2_ACS_FAIL_ADDR
  243. L1_ICACHE2_ACS_FAIL_ID_ATTR
  244. L1_ICACHE2_ACS_FAIL_ID_ATTR
  245. L1_ICACHE2_AUTOLOAD_CTRL
  246. L1_ICACHE2_AUTOLOAD_CTRL
  247. L1_ICACHE2_AUTOLOAD_SCT0_ADDR
  248. L1_ICACHE2_AUTOLOAD_SCT0_ADDR
  249. L1_ICACHE2_AUTOLOAD_SCT0_SIZE
  250. L1_ICACHE2_AUTOLOAD_SCT0_SIZE
  251. L1_ICACHE2_AUTOLOAD_SCT1_ADDR
  252. L1_ICACHE2_AUTOLOAD_SCT1_ADDR
  253. L1_ICACHE2_AUTOLOAD_SCT1_SIZE
  254. L1_ICACHE2_AUTOLOAD_SCT1_SIZE
  255. L1_ICACHE2_PRELOAD_ADDR
  256. L1_ICACHE2_PRELOAD_ADDR
  257. L1_ICACHE2_PRELOAD_CTRL
  258. L1_ICACHE2_PRELOAD_CTRL
  259. L1_ICACHE2_PRELOAD_SIZE
  260. L1_ICACHE2_PRELOAD_SIZE
  261. L1_ICACHE2_PRELOCK_CONF
  262. L1_ICACHE2_PRELOCK_CONF
  263. L1_ICACHE2_PRELOCK_SCT0_ADDR
  264. L1_ICACHE2_PRELOCK_SCT0_ADDR
  265. L1_ICACHE2_PRELOCK_SCT1_ADDR
  266. L1_ICACHE2_PRELOCK_SCT1_ADDR
  267. L1_ICACHE2_PRELOCK_SCT_SIZE
  268. L1_ICACHE2_PRELOCK_SCT_SIZE
  269. L1_ICACHE3_ACS_FAIL_ADDR
  270. L1_ICACHE3_ACS_FAIL_ADDR
  271. L1_ICACHE3_ACS_FAIL_ID_ATTR
  272. L1_ICACHE3_ACS_FAIL_ID_ATTR
  273. L1_ICACHE3_AUTOLOAD_CTRL
  274. L1_ICACHE3_AUTOLOAD_CTRL
  275. L1_ICACHE3_AUTOLOAD_SCT0_ADDR
  276. L1_ICACHE3_AUTOLOAD_SCT0_ADDR
  277. L1_ICACHE3_AUTOLOAD_SCT0_SIZE
  278. L1_ICACHE3_AUTOLOAD_SCT0_SIZE
  279. L1_ICACHE3_AUTOLOAD_SCT1_ADDR
  280. L1_ICACHE3_AUTOLOAD_SCT1_ADDR
  281. L1_ICACHE3_AUTOLOAD_SCT1_SIZE
  282. L1_ICACHE3_AUTOLOAD_SCT1_SIZE
  283. L1_ICACHE3_PRELOAD_ADDR
  284. L1_ICACHE3_PRELOAD_ADDR
  285. L1_ICACHE3_PRELOAD_CTRL
  286. L1_ICACHE3_PRELOAD_CTRL
  287. L1_ICACHE3_PRELOAD_SIZE
  288. L1_ICACHE3_PRELOAD_SIZE
  289. L1_ICACHE3_PRELOCK_CONF
  290. L1_ICACHE3_PRELOCK_CONF
  291. L1_ICACHE3_PRELOCK_SCT0_ADDR
  292. L1_ICACHE3_PRELOCK_SCT0_ADDR
  293. L1_ICACHE3_PRELOCK_SCT1_ADDR
  294. L1_ICACHE3_PRELOCK_SCT1_ADDR
  295. L1_ICACHE3_PRELOCK_SCT_SIZE
  296. L1_ICACHE3_PRELOCK_SCT_SIZE
  297. L1_ICACHE_BLOCKSIZE_CONF
  298. L1_ICACHE_BLOCKSIZE_CONF
  299. L1_ICACHE_CACHESIZE_CONF
  300. L1_ICACHE_CACHESIZE_CONF
  301. L1_ICACHE_CTRL
  302. L1_ICACHE_CTRL
  303. L1_UNALLOCATE_BUFFER_CLEAR
  304. L1_UNALLOCATE_BUFFER_CLEAR
  305. L2_BYPASS_CACHE_CONF
  306. L2_BYPASS_CACHE_CONF
  307. L2_CACHE_ACCESS_ATTR_CTRL
  308. L2_CACHE_ACCESS_ATTR_CTRL
  309. L2_CACHE_ACS_CNT_CTRL
  310. L2_CACHE_ACS_CNT_CTRL
  311. L2_CACHE_ACS_CNT_INT_CLR
  312. L2_CACHE_ACS_CNT_INT_CLR
  313. L2_CACHE_ACS_CNT_INT_ENA
  314. L2_CACHE_ACS_CNT_INT_ENA
  315. L2_CACHE_ACS_CNT_INT_RAW
  316. L2_CACHE_ACS_CNT_INT_RAW
  317. L2_CACHE_ACS_CNT_INT_ST
  318. L2_CACHE_ACS_CNT_INT_ST
  319. L2_CACHE_ACS_FAIL_ADDR
  320. L2_CACHE_ACS_FAIL_ADDR
  321. L2_CACHE_ACS_FAIL_ID_ATTR
  322. L2_CACHE_ACS_FAIL_ID_ATTR
  323. L2_CACHE_ACS_FAIL_INT_CLR
  324. L2_CACHE_ACS_FAIL_INT_CLR
  325. L2_CACHE_ACS_FAIL_INT_ENA
  326. L2_CACHE_ACS_FAIL_INT_ENA
  327. L2_CACHE_ACS_FAIL_INT_RAW
  328. L2_CACHE_ACS_FAIL_INT_RAW
  329. L2_CACHE_ACS_FAIL_INT_ST
  330. L2_CACHE_ACS_FAIL_INT_ST
  331. L2_CACHE_AUTOLOAD_BUF_CLR_CTRL
  332. L2_CACHE_AUTOLOAD_BUF_CLR_CTRL
  333. L2_CACHE_AUTOLOAD_CTRL
  334. L2_CACHE_AUTOLOAD_CTRL
  335. L2_CACHE_AUTOLOAD_SCT0_ADDR
  336. L2_CACHE_AUTOLOAD_SCT0_ADDR
  337. L2_CACHE_AUTOLOAD_SCT0_SIZE
  338. L2_CACHE_AUTOLOAD_SCT0_SIZE
  339. L2_CACHE_AUTOLOAD_SCT1_ADDR
  340. L2_CACHE_AUTOLOAD_SCT1_ADDR
  341. L2_CACHE_AUTOLOAD_SCT1_SIZE
  342. L2_CACHE_AUTOLOAD_SCT1_SIZE
  343. L2_CACHE_AUTOLOAD_SCT2_ADDR
  344. L2_CACHE_AUTOLOAD_SCT2_ADDR
  345. L2_CACHE_AUTOLOAD_SCT2_SIZE
  346. L2_CACHE_AUTOLOAD_SCT2_SIZE
  347. L2_CACHE_AUTOLOAD_SCT3_ADDR
  348. L2_CACHE_AUTOLOAD_SCT3_ADDR
  349. L2_CACHE_AUTOLOAD_SCT3_SIZE
  350. L2_CACHE_AUTOLOAD_SCT3_SIZE
  351. L2_CACHE_BLOCKSIZE_CONF
  352. L2_CACHE_BLOCKSIZE_CONF
  353. L2_CACHE_CACHESIZE_CONF
  354. L2_CACHE_CACHESIZE_CONF
  355. L2_CACHE_CTRL
  356. L2_CACHE_CTRL
  357. L2_CACHE_DATA_MEM_ACS_CONF
  358. L2_CACHE_DATA_MEM_ACS_CONF
  359. L2_CACHE_DATA_MEM_POWER_CTRL
  360. L2_CACHE_DATA_MEM_POWER_CTRL
  361. L2_CACHE_DEBUG_BUS
  362. L2_CACHE_DEBUG_BUS
  363. L2_CACHE_FREEZE_CTRL
  364. L2_CACHE_FREEZE_CTRL
  365. L2_CACHE_OBJECT_CTRL
  366. L2_CACHE_OBJECT_CTRL
  367. L2_CACHE_PRELOAD_ADDR
  368. L2_CACHE_PRELOAD_ADDR
  369. L2_CACHE_PRELOAD_CTRL
  370. L2_CACHE_PRELOAD_CTRL
  371. L2_CACHE_PRELOAD_RST_CTRL
  372. L2_CACHE_PRELOAD_RST_CTRL
  373. L2_CACHE_PRELOAD_SIZE
  374. L2_CACHE_PRELOAD_SIZE
  375. L2_CACHE_PRELOCK_CONF
  376. L2_CACHE_PRELOCK_CONF
  377. L2_CACHE_PRELOCK_SCT0_ADDR
  378. L2_CACHE_PRELOCK_SCT0_ADDR
  379. L2_CACHE_PRELOCK_SCT1_ADDR
  380. L2_CACHE_PRELOCK_SCT1_ADDR
  381. L2_CACHE_PRELOCK_SCT_SIZE
  382. L2_CACHE_PRELOCK_SCT_SIZE
  383. L2_CACHE_SYNC_PRELOAD_EXCEPTION
  384. L2_CACHE_SYNC_PRELOAD_EXCEPTION
  385. L2_CACHE_SYNC_PRELOAD_INT_CLR
  386. L2_CACHE_SYNC_PRELOAD_INT_CLR
  387. L2_CACHE_SYNC_PRELOAD_INT_ENA
  388. L2_CACHE_SYNC_PRELOAD_INT_ENA
  389. L2_CACHE_SYNC_PRELOAD_INT_RAW
  390. L2_CACHE_SYNC_PRELOAD_INT_RAW
  391. L2_CACHE_SYNC_PRELOAD_INT_ST
  392. L2_CACHE_SYNC_PRELOAD_INT_ST
  393. L2_CACHE_SYNC_RST_CTRL
  394. L2_CACHE_SYNC_RST_CTRL
  395. L2_CACHE_TAG_MEM_ACS_CONF
  396. L2_CACHE_TAG_MEM_ACS_CONF
  397. L2_CACHE_TAG_MEM_POWER_CTRL
  398. L2_CACHE_TAG_MEM_POWER_CTRL
  399. L2_CACHE_VADDR
  400. L2_CACHE_VADDR
  401. L2_CACHE_WAY_OBJECT
  402. L2_CACHE_WAY_OBJECT
  403. L2_CACHE_WRAP_AROUND_CTRL
  404. L2_CACHE_WRAP_AROUND_CTRL
  405. L2_DBUS0_ACS_CONFLICT_CNT
  406. L2_DBUS0_ACS_CONFLICT_CNT
  407. L2_DBUS0_ACS_HIT_CNT
  408. L2_DBUS0_ACS_HIT_CNT
  409. L2_DBUS0_ACS_MISS_CNT
  410. L2_DBUS0_ACS_MISS_CNT
  411. L2_DBUS0_ACS_NXTLVL_CNT
  412. L2_DBUS0_ACS_NXTLVL_CNT
  413. L2_DBUS1_ACS_CONFLICT_CNT
  414. L2_DBUS1_ACS_CONFLICT_CNT
  415. L2_DBUS1_ACS_HIT_CNT
  416. L2_DBUS1_ACS_HIT_CNT
  417. L2_DBUS1_ACS_MISS_CNT
  418. L2_DBUS1_ACS_MISS_CNT
  419. L2_DBUS1_ACS_NXTLVL_CNT
  420. L2_DBUS1_ACS_NXTLVL_CNT
  421. L2_DBUS2_ACS_CONFLICT_CNT
  422. L2_DBUS2_ACS_CONFLICT_CNT
  423. L2_DBUS2_ACS_HIT_CNT
  424. L2_DBUS2_ACS_HIT_CNT
  425. L2_DBUS2_ACS_MISS_CNT
  426. L2_DBUS2_ACS_MISS_CNT
  427. L2_DBUS2_ACS_NXTLVL_CNT
  428. L2_DBUS2_ACS_NXTLVL_CNT
  429. L2_DBUS3_ACS_CONFLICT_CNT
  430. L2_DBUS3_ACS_CONFLICT_CNT
  431. L2_DBUS3_ACS_HIT_CNT
  432. L2_DBUS3_ACS_HIT_CNT
  433. L2_DBUS3_ACS_MISS_CNT
  434. L2_DBUS3_ACS_MISS_CNT
  435. L2_DBUS3_ACS_NXTLVL_CNT
  436. L2_DBUS3_ACS_NXTLVL_CNT
  437. L2_IBUS0_ACS_CONFLICT_CNT
  438. L2_IBUS0_ACS_CONFLICT_CNT
  439. L2_IBUS0_ACS_HIT_CNT
  440. L2_IBUS0_ACS_HIT_CNT
  441. L2_IBUS0_ACS_MISS_CNT
  442. L2_IBUS0_ACS_MISS_CNT
  443. L2_IBUS0_ACS_NXTLVL_CNT
  444. L2_IBUS0_ACS_NXTLVL_CNT
  445. L2_IBUS1_ACS_CONFLICT_CNT
  446. L2_IBUS1_ACS_CONFLICT_CNT
  447. L2_IBUS1_ACS_HIT_CNT
  448. L2_IBUS1_ACS_HIT_CNT
  449. L2_IBUS1_ACS_MISS_CNT
  450. L2_IBUS1_ACS_MISS_CNT
  451. L2_IBUS1_ACS_NXTLVL_CNT
  452. L2_IBUS1_ACS_NXTLVL_CNT
  453. L2_IBUS2_ACS_CONFLICT_CNT
  454. L2_IBUS2_ACS_CONFLICT_CNT
  455. L2_IBUS2_ACS_HIT_CNT
  456. L2_IBUS2_ACS_HIT_CNT
  457. L2_IBUS2_ACS_MISS_CNT
  458. L2_IBUS2_ACS_MISS_CNT
  459. L2_IBUS2_ACS_NXTLVL_CNT
  460. L2_IBUS2_ACS_NXTLVL_CNT
  461. L2_IBUS3_ACS_CONFLICT_CNT
  462. L2_IBUS3_ACS_CONFLICT_CNT
  463. L2_IBUS3_ACS_HIT_CNT
  464. L2_IBUS3_ACS_HIT_CNT
  465. L2_IBUS3_ACS_MISS_CNT
  466. L2_IBUS3_ACS_MISS_CNT
  467. L2_IBUS3_ACS_NXTLVL_CNT
  468. L2_IBUS3_ACS_NXTLVL_CNT
  469. L2_UNALLOCATE_BUFFER_CLEAR
  470. L2_UNALLOCATE_BUFFER_CLEAR
  471. LEVEL_SPLIT0
  472. LEVEL_SPLIT0
  473. LEVEL_SPLIT1
  474. LEVEL_SPLIT1
  475. REDUNDANCY_SIG0
  476. REDUNDANCY_SIG0
  477. REDUNDANCY_SIG1
  478. REDUNDANCY_SIG1
  479. REDUNDANCY_SIG2
  480. REDUNDANCY_SIG2
  481. REDUNDANCY_SIG3
  482. REDUNDANCY_SIG3
  483. REDUNDANCY_SIG4
  484. REDUNDANCY_SIG4