Regviz

Browse Registers In Our Database

Browse below to find the registers you are looking for, or search for one. For each register you can visualize its contents, and for many there is some basic reference information.

Registers in Espressif Systems /ESP32-P4 /AHB_DMA

  1. AHB_TEST
  2. AHB_TEST
  3. ARB_TIMEOUT_RX
  4. ARB_TIMEOUT_RX
  5. ARB_TIMEOUT_TX
  6. ARB_TIMEOUT_TX
  7. DATE
  8. DATE
  9. IN_CONF0_CH0
  10. IN_CONF0_CH0
  11. IN_CONF0_CH1
  12. IN_CONF0_CH1
  13. IN_CONF0_CH2
  14. IN_CONF0_CH2
  15. IN_CONF1_CH0
  16. IN_CONF1_CH0
  17. IN_CONF1_CH1
  18. IN_CONF1_CH1
  19. IN_CONF1_CH2
  20. IN_CONF1_CH2
  21. IN_CRC_CLEAR_CH0
  22. IN_CRC_CLEAR_CH0
  23. IN_CRC_CLEAR_CH1
  24. IN_CRC_CLEAR_CH1
  25. IN_CRC_CLEAR_CH2
  26. IN_CRC_CLEAR_CH2
  27. IN_CRC_FINAL_RESULT_CH0
  28. IN_CRC_FINAL_RESULT_CH0
  29. IN_CRC_FINAL_RESULT_CH1
  30. IN_CRC_FINAL_RESULT_CH1
  31. IN_CRC_FINAL_RESULT_CH2
  32. IN_CRC_FINAL_RESULT_CH2
  33. IN_CRC_INIT_DATA_CH0
  34. IN_CRC_INIT_DATA_CH0
  35. IN_CRC_INIT_DATA_CH1
  36. IN_CRC_INIT_DATA_CH1
  37. IN_CRC_INIT_DATA_CH2
  38. IN_CRC_INIT_DATA_CH2
  39. IN_DSCR_BF0_CH0
  40. IN_DSCR_BF0_CH0
  41. IN_DSCR_BF0_CH1
  42. IN_DSCR_BF0_CH1
  43. IN_DSCR_BF0_CH2
  44. IN_DSCR_BF0_CH2
  45. IN_DSCR_BF1_CH0
  46. IN_DSCR_BF1_CH0
  47. IN_DSCR_BF1_CH1
  48. IN_DSCR_BF1_CH1
  49. IN_DSCR_BF1_CH2
  50. IN_DSCR_BF1_CH2
  51. IN_DSCR_CH0
  52. IN_DSCR_CH0
  53. IN_DSCR_CH1
  54. IN_DSCR_CH1
  55. IN_DSCR_CH2
  56. IN_DSCR_CH2
  57. IN_ERR_EOF_DES_ADDR_CH0
  58. IN_ERR_EOF_DES_ADDR_CH0
  59. IN_ERR_EOF_DES_ADDR_CH1
  60. IN_ERR_EOF_DES_ADDR_CH1
  61. IN_ERR_EOF_DES_ADDR_CH2
  62. IN_ERR_EOF_DES_ADDR_CH2
  63. INFIFO_STATUS_CH0
  64. INFIFO_STATUS_CH0
  65. INFIFO_STATUS_CH1
  66. INFIFO_STATUS_CH1
  67. INFIFO_STATUS_CH2
  68. INFIFO_STATUS_CH2
  69. IN_INT_CLR_CH0
  70. IN_INT_CLR_CH0
  71. IN_INT_CLR_CH1
  72. IN_INT_CLR_CH1
  73. IN_INT_CLR_CH2
  74. IN_INT_CLR_CH2
  75. IN_INT_ENA_CH0
  76. IN_INT_ENA_CH0
  77. IN_INT_ENA_CH1
  78. IN_INT_ENA_CH1
  79. IN_INT_ENA_CH2
  80. IN_INT_ENA_CH2
  81. IN_INT_RAW_CH0
  82. IN_INT_RAW_CH0
  83. IN_INT_RAW_CH1
  84. IN_INT_RAW_CH1
  85. IN_INT_RAW_CH2
  86. IN_INT_RAW_CH2
  87. IN_INT_ST_CH0
  88. IN_INT_ST_CH0
  89. IN_INT_ST_CH1
  90. IN_INT_ST_CH1
  91. IN_INT_ST_CH2
  92. IN_INT_ST_CH2
  93. IN_LINK_ADDR_CH0
  94. IN_LINK_ADDR_CH0
  95. IN_LINK_ADDR_CH1
  96. IN_LINK_ADDR_CH1
  97. IN_LINK_ADDR_CH2
  98. IN_LINK_ADDR_CH2
  99. IN_LINK_CH0
  100. IN_LINK_CH0
  101. IN_LINK_CH1
  102. IN_LINK_CH1
  103. IN_LINK_CH2
  104. IN_LINK_CH2
  105. IN_PERI_SEL_CH0
  106. IN_PERI_SEL_CH0
  107. IN_PERI_SEL_CH1
  108. IN_PERI_SEL_CH1
  109. IN_PERI_SEL_CH2
  110. IN_PERI_SEL_CH2
  111. IN_POP_CH0
  112. IN_POP_CH0
  113. IN_POP_CH1
  114. IN_POP_CH1
  115. IN_POP_CH2
  116. IN_POP_CH2
  117. IN_PRI_CH0
  118. IN_PRI_CH0
  119. IN_PRI_CH1
  120. IN_PRI_CH1
  121. IN_PRI_CH2
  122. IN_PRI_CH2
  123. IN_STATE_CH0
  124. IN_STATE_CH0
  125. IN_STATE_CH1
  126. IN_STATE_CH1
  127. IN_STATE_CH2
  128. IN_STATE_CH2
  129. IN_SUC_EOF_DES_ADDR_CH0
  130. IN_SUC_EOF_DES_ADDR_CH0
  131. IN_SUC_EOF_DES_ADDR_CH1
  132. IN_SUC_EOF_DES_ADDR_CH1
  133. IN_SUC_EOF_DES_ADDR_CH2
  134. IN_SUC_EOF_DES_ADDR_CH2
  135. INTR_MEM_END_ADDR
  136. INTR_MEM_END_ADDR
  137. INTR_MEM_START_ADDR
  138. INTR_MEM_START_ADDR
  139. MISC_CONF
  140. MISC_CONF
  141. OUT_CONF0_CH0
  142. OUT_CONF0_CH0
  143. OUT_CONF0_CH0
  144. OUT_CONF0_CH0
  145. OUT_CONF0_CH1
  146. OUT_CONF0_CH1
  147. OUT_CONF1_CH0
  148. OUT_CONF1_CH0
  149. OUT_CONF1_CH1
  150. OUT_CONF1_CH1
  151. OUT_CONF1_CH2
  152. OUT_CONF1_CH2
  153. OUT_CRC_CLEAR_CH0
  154. OUT_CRC_CLEAR_CH0
  155. OUT_CRC_CLEAR_CH1
  156. OUT_CRC_CLEAR_CH1
  157. OUT_CRC_CLEAR_CH2
  158. OUT_CRC_CLEAR_CH2
  159. OUT_CRC_FINAL_RESULT_CH0
  160. OUT_CRC_FINAL_RESULT_CH0
  161. OUT_CRC_FINAL_RESULT_CH1
  162. OUT_CRC_FINAL_RESULT_CH1
  163. OUT_CRC_FINAL_RESULT_CH2
  164. OUT_CRC_FINAL_RESULT_CH2
  165. OUT_CRC_INIT_DATA_CH0
  166. OUT_CRC_INIT_DATA_CH0
  167. OUT_CRC_INIT_DATA_CH1
  168. OUT_CRC_INIT_DATA_CH1
  169. OUT_CRC_INIT_DATA_CH2
  170. OUT_CRC_INIT_DATA_CH2
  171. OUT_DSCR_BF0_CH0
  172. OUT_DSCR_BF0_CH0
  173. OUT_DSCR_BF0_CH1
  174. OUT_DSCR_BF0_CH1
  175. OUT_DSCR_BF0_CH2
  176. OUT_DSCR_BF0_CH2
  177. OUT_DSCR_BF1_CH0
  178. OUT_DSCR_BF1_CH0
  179. OUT_DSCR_BF1_CH1
  180. OUT_DSCR_BF1_CH1
  181. OUT_DSCR_BF1_CH2
  182. OUT_DSCR_BF1_CH2
  183. OUT_DSCR_CH0
  184. OUT_DSCR_CH0
  185. OUT_DSCR_CH1
  186. OUT_DSCR_CH1
  187. OUT_DSCR_CH2
  188. OUT_DSCR_CH2
  189. OUT_EOF_BFR_DES_ADDR_CH0
  190. OUT_EOF_BFR_DES_ADDR_CH0
  191. OUT_EOF_BFR_DES_ADDR_CH1
  192. OUT_EOF_BFR_DES_ADDR_CH1
  193. OUT_EOF_BFR_DES_ADDR_CH2
  194. OUT_EOF_BFR_DES_ADDR_CH2
  195. OUT_EOF_DES_ADDR_CH0
  196. OUT_EOF_DES_ADDR_CH0
  197. OUT_EOF_DES_ADDR_CH1
  198. OUT_EOF_DES_ADDR_CH1
  199. OUT_EOF_DES_ADDR_CH2
  200. OUT_EOF_DES_ADDR_CH2
  201. OUTFIFO_STATUS_CH0
  202. OUTFIFO_STATUS_CH0
  203. OUTFIFO_STATUS_CH1
  204. OUTFIFO_STATUS_CH1
  205. OUTFIFO_STATUS_CH2
  206. OUTFIFO_STATUS_CH2
  207. OUT_INT_CLR_CH0
  208. OUT_INT_CLR_CH0
  209. OUT_INT_CLR_CH1
  210. OUT_INT_CLR_CH1
  211. OUT_INT_CLR_CH2
  212. OUT_INT_CLR_CH2
  213. OUT_INT_ENA_CH0
  214. OUT_INT_ENA_CH0
  215. OUT_INT_ENA_CH1
  216. OUT_INT_ENA_CH1
  217. OUT_INT_ENA_CH2
  218. OUT_INT_ENA_CH2
  219. OUT_INT_RAW_CH0
  220. OUT_INT_RAW_CH0
  221. OUT_INT_RAW_CH1
  222. OUT_INT_RAW_CH1
  223. OUT_INT_RAW_CH2
  224. OUT_INT_RAW_CH2
  225. OUT_INT_ST_CH0
  226. OUT_INT_ST_CH0
  227. OUT_INT_ST_CH1
  228. OUT_INT_ST_CH1
  229. OUT_INT_ST_CH2
  230. OUT_INT_ST_CH2
  231. OUT_LINK_ADDR_CH0
  232. OUT_LINK_ADDR_CH0
  233. OUT_LINK_ADDR_CH1
  234. OUT_LINK_ADDR_CH1
  235. OUT_LINK_ADDR_CH2
  236. OUT_LINK_ADDR_CH2
  237. OUT_LINK_CH0
  238. OUT_LINK_CH0
  239. OUT_LINK_CH1
  240. OUT_LINK_CH1
  241. OUT_LINK_CH2
  242. OUT_LINK_CH2
  243. OUT_PERI_SEL_CH0
  244. OUT_PERI_SEL_CH0
  245. OUT_PERI_SEL_CH1
  246. OUT_PERI_SEL_CH1
  247. OUT_PERI_SEL_CH2
  248. OUT_PERI_SEL_CH2
  249. OUT_PRI_CH0
  250. OUT_PRI_CH0
  251. OUT_PRI_CH1
  252. OUT_PRI_CH1
  253. OUT_PRI_CH2
  254. OUT_PRI_CH2
  255. OUT_PUSH_CH0
  256. OUT_PUSH_CH0
  257. OUT_PUSH_CH1
  258. OUT_PUSH_CH1
  259. OUT_PUSH_CH2
  260. OUT_PUSH_CH2
  261. OUT_STATE_CH0
  262. OUT_STATE_CH0
  263. OUT_STATE_CH1
  264. OUT_STATE_CH1
  265. OUT_STATE_CH2
  266. OUT_STATE_CH2
  267. RX_ARB_WEIGH_OPT_DIR_CH0
  268. RX_ARB_WEIGH_OPT_DIR_CH0
  269. RX_ARB_WEIGH_OPT_DIR_CH1
  270. RX_ARB_WEIGH_OPT_DIR_CH1
  271. RX_ARB_WEIGH_OPT_DIR_CH2
  272. RX_ARB_WEIGH_OPT_DIR_CH2
  273. RX_CH_ARB_WEIGH_CH0
  274. RX_CH_ARB_WEIGH_CH0
  275. RX_CH_ARB_WEIGH_CH1
  276. RX_CH_ARB_WEIGH_CH1
  277. RX_CH_ARB_WEIGH_CH2
  278. RX_CH_ARB_WEIGH_CH2
  279. RX_CRC_DATA_EN_ADDR_CH0
  280. RX_CRC_DATA_EN_ADDR_CH0
  281. RX_CRC_DATA_EN_ADDR_CH1
  282. RX_CRC_DATA_EN_ADDR_CH1
  283. RX_CRC_DATA_EN_ADDR_CH2
  284. RX_CRC_DATA_EN_ADDR_CH2
  285. RX_CRC_DATA_EN_WR_DATA_CH0
  286. RX_CRC_DATA_EN_WR_DATA_CH0
  287. RX_CRC_DATA_EN_WR_DATA_CH1
  288. RX_CRC_DATA_EN_WR_DATA_CH1
  289. RX_CRC_DATA_EN_WR_DATA_CH2
  290. RX_CRC_DATA_EN_WR_DATA_CH2
  291. RX_CRC_EN_ADDR_CH0
  292. RX_CRC_EN_ADDR_CH0
  293. RX_CRC_EN_ADDR_CH1
  294. RX_CRC_EN_ADDR_CH1
  295. RX_CRC_EN_ADDR_CH2
  296. RX_CRC_EN_ADDR_CH2
  297. RX_CRC_EN_WR_DATA_CH0
  298. RX_CRC_EN_WR_DATA_CH0
  299. RX_CRC_EN_WR_DATA_CH1
  300. RX_CRC_EN_WR_DATA_CH1
  301. RX_CRC_EN_WR_DATA_CH2
  302. RX_CRC_EN_WR_DATA_CH2
  303. RX_CRC_WIDTH_CH0
  304. RX_CRC_WIDTH_CH0
  305. RX_CRC_WIDTH_CH1
  306. RX_CRC_WIDTH_CH1
  307. RX_CRC_WIDTH_CH2
  308. RX_CRC_WIDTH_CH2
  309. TX_ARB_WEIGH_OPT_DIR_CH0
  310. TX_ARB_WEIGH_OPT_DIR_CH0
  311. TX_ARB_WEIGH_OPT_DIR_CH1
  312. TX_ARB_WEIGH_OPT_DIR_CH1
  313. TX_ARB_WEIGH_OPT_DIR_CH2
  314. TX_ARB_WEIGH_OPT_DIR_CH2
  315. TX_CH_ARB_WEIGH_CH0
  316. TX_CH_ARB_WEIGH_CH0
  317. TX_CH_ARB_WEIGH_CH1
  318. TX_CH_ARB_WEIGH_CH1
  319. TX_CH_ARB_WEIGH_CH2
  320. TX_CH_ARB_WEIGH_CH2
  321. TX_CRC_DATA_EN_ADDR_CH0
  322. TX_CRC_DATA_EN_ADDR_CH0
  323. TX_CRC_DATA_EN_ADDR_CH1
  324. TX_CRC_DATA_EN_ADDR_CH1
  325. TX_CRC_DATA_EN_ADDR_CH2
  326. TX_CRC_DATA_EN_ADDR_CH2
  327. TX_CRC_DATA_EN_WR_DATA_CH0
  328. TX_CRC_DATA_EN_WR_DATA_CH0
  329. TX_CRC_DATA_EN_WR_DATA_CH1
  330. TX_CRC_DATA_EN_WR_DATA_CH1
  331. TX_CRC_DATA_EN_WR_DATA_CH2
  332. TX_CRC_DATA_EN_WR_DATA_CH2
  333. TX_CRC_EN_ADDR_CH0
  334. TX_CRC_EN_ADDR_CH0
  335. TX_CRC_EN_ADDR_CH1
  336. TX_CRC_EN_ADDR_CH1
  337. TX_CRC_EN_ADDR_CH2
  338. TX_CRC_EN_ADDR_CH2
  339. TX_CRC_EN_WR_DATA_CH0
  340. TX_CRC_EN_WR_DATA_CH0
  341. TX_CRC_EN_WR_DATA_CH1
  342. TX_CRC_EN_WR_DATA_CH1
  343. TX_CRC_EN_WR_DATA_CH2
  344. TX_CRC_EN_WR_DATA_CH2
  345. TX_CRC_WIDTH_CH0
  346. TX_CRC_WIDTH_CH0
  347. TX_CRC_WIDTH_CH1
  348. TX_CRC_WIDTH_CH1
  349. TX_CRC_WIDTH_CH2
  350. TX_CRC_WIDTH_CH2
  351. WEIGHT_EN_RX
  352. WEIGHT_EN_RX
  353. WEIGHT_EN_TX
  354. WEIGHT_EN_TX