Regviz

Browse Registers In Our Database

Browse below to find the registers you are looking for, or search for one. For each register you can visualize its contents, and for many there is some basic reference information.

Registers in Espressif Systems /ESP32-P4 /AXI_DMA

  1. ARB_TIMEOUT
  2. ARB_TIMEOUT
  3. DATE
  4. DATE
  5. EXTR_MEM_END_ADDR
  6. EXTR_MEM_END_ADDR
  7. EXTR_MEM_START_ADDR
  8. EXTR_MEM_START_ADDR
  9. IN_CONF0_CH0
  10. IN_CONF0_CH0
  11. IN_CONF0_CH1
  12. IN_CONF0_CH1
  13. IN_CONF0_CH2
  14. IN_CONF0_CH2
  15. IN_CONF1_CH0
  16. IN_CONF1_CH0
  17. IN_CONF1_CH1
  18. IN_CONF1_CH1
  19. IN_CONF1_CH2
  20. IN_CONF1_CH2
  21. IN_CRC_CLEAR_CH0
  22. IN_CRC_CLEAR_CH0
  23. IN_CRC_CLEAR_CH1
  24. IN_CRC_CLEAR_CH1
  25. IN_CRC_CLEAR_CH2
  26. IN_CRC_CLEAR_CH2
  27. IN_CRC_FINAL_RESULT_CH0
  28. IN_CRC_FINAL_RESULT_CH0
  29. IN_CRC_FINAL_RESULT_CH1
  30. IN_CRC_FINAL_RESULT_CH1
  31. IN_CRC_FINAL_RESULT_CH2
  32. IN_CRC_FINAL_RESULT_CH2
  33. IN_CRC_INIT_DATA_CH0
  34. IN_CRC_INIT_DATA_CH0
  35. IN_CRC_INIT_DATA_CH1
  36. IN_CRC_INIT_DATA_CH1
  37. IN_CRC_INIT_DATA_CH2
  38. IN_CRC_INIT_DATA_CH2
  39. IN_DSCR_BF0_CH0
  40. IN_DSCR_BF0_CH0
  41. IN_DSCR_BF0_CH1
  42. IN_DSCR_BF0_CH1
  43. IN_DSCR_BF0_CH2
  44. IN_DSCR_BF0_CH2
  45. IN_DSCR_BF1_CH0
  46. IN_DSCR_BF1_CH0
  47. IN_DSCR_BF1_CH1
  48. IN_DSCR_BF1_CH1
  49. IN_DSCR_BF1_CH2
  50. IN_DSCR_BF1_CH2
  51. IN_DSCR_CH0
  52. IN_DSCR_CH0
  53. IN_DSCR_CH1
  54. IN_DSCR_CH1
  55. IN_DSCR_CH2
  56. IN_DSCR_CH2
  57. IN_ERR_EOF_DES_ADDR_CH0
  58. IN_ERR_EOF_DES_ADDR_CH0
  59. IN_ERR_EOF_DES_ADDR_CH1
  60. IN_ERR_EOF_DES_ADDR_CH1
  61. IN_ERR_EOF_DES_ADDR_CH2
  62. IN_ERR_EOF_DES_ADDR_CH2
  63. INFIFO_STATUS1_CH0
  64. INFIFO_STATUS1_CH0
  65. INFIFO_STATUS1_CH1
  66. INFIFO_STATUS1_CH1
  67. INFIFO_STATUS1_CH2
  68. INFIFO_STATUS1_CH2
  69. INFIFO_STATUS_CH0
  70. INFIFO_STATUS_CH0
  71. INFIFO_STATUS_CH1
  72. INFIFO_STATUS_CH1
  73. INFIFO_STATUS_CH2
  74. INFIFO_STATUS_CH2
  75. IN_INT_CLR_CH0
  76. IN_INT_CLR_CH0
  77. IN_INT_CLR_CH1
  78. IN_INT_CLR_CH1
  79. IN_INT_CLR_CH2
  80. IN_INT_CLR_CH2
  81. IN_INT_ENA_CH0
  82. IN_INT_ENA_CH0
  83. IN_INT_ENA_CH1
  84. IN_INT_ENA_CH1
  85. IN_INT_ENA_CH2
  86. IN_INT_ENA_CH2
  87. IN_INT_RAW_CH0
  88. IN_INT_RAW_CH0
  89. IN_INT_RAW_CH1
  90. IN_INT_RAW_CH1
  91. IN_INT_RAW_CH2
  92. IN_INT_RAW_CH2
  93. IN_INT_ST_CH0
  94. IN_INT_ST_CH0
  95. IN_INT_ST_CH1
  96. IN_INT_ST_CH1
  97. IN_INT_ST_CH2
  98. IN_INT_ST_CH2
  99. IN_LINK1_CH0
  100. IN_LINK1_CH0
  101. IN_LINK1_CH1
  102. IN_LINK1_CH1
  103. IN_LINK1_CH2
  104. IN_LINK1_CH2
  105. IN_LINK2_CH0
  106. IN_LINK2_CH0
  107. IN_LINK2_CH1
  108. IN_LINK2_CH1
  109. IN_LINK2_CH2
  110. IN_LINK2_CH2
  111. IN_MEM_CONF
  112. IN_MEM_CONF
  113. IN_PERI_SEL_CH0
  114. IN_PERI_SEL_CH0
  115. IN_PERI_SEL_CH1
  116. IN_PERI_SEL_CH1
  117. IN_PERI_SEL_CH2
  118. IN_PERI_SEL_CH2
  119. IN_POP_CH0
  120. IN_POP_CH0
  121. IN_POP_CH1
  122. IN_POP_CH1
  123. IN_POP_CH2
  124. IN_POP_CH2
  125. IN_PRI_CH0
  126. IN_PRI_CH0
  127. IN_PRI_CH1
  128. IN_PRI_CH1
  129. IN_PRI_CH2
  130. IN_PRI_CH2
  131. IN_RESET_AVAIL_CH0
  132. IN_RESET_AVAIL_CH0
  133. IN_RESET_AVAIL_CH1
  134. IN_RESET_AVAIL_CH1
  135. IN_RESET_AVAIL_CH2
  136. IN_RESET_AVAIL_CH2
  137. IN_STATE_CH0
  138. IN_STATE_CH0
  139. IN_STATE_CH1
  140. IN_STATE_CH1
  141. IN_STATE_CH2
  142. IN_STATE_CH2
  143. IN_SUC_EOF_DES_ADDR_CH0
  144. IN_SUC_EOF_DES_ADDR_CH0
  145. IN_SUC_EOF_DES_ADDR_CH1
  146. IN_SUC_EOF_DES_ADDR_CH1
  147. IN_SUC_EOF_DES_ADDR_CH2
  148. IN_SUC_EOF_DES_ADDR_CH2
  149. INTR_MEM_END_ADDR
  150. INTR_MEM_END_ADDR
  151. INTR_MEM_START_ADDR
  152. INTR_MEM_START_ADDR
  153. MISC_CONF
  154. MISC_CONF
  155. OUT_CONF0_CH0
  156. OUT_CONF0_CH0
  157. OUT_CONF0_CH1
  158. OUT_CONF0_CH1
  159. OUT_CONF0_CH2
  160. OUT_CONF0_CH2
  161. OUT_CONF1_CH0
  162. OUT_CONF1_CH0
  163. OUT_CONF1_CH1
  164. OUT_CONF1_CH1
  165. OUT_CONF1_CH2
  166. OUT_CONF1_CH2
  167. OUT_CRC_CLEAR_CH0
  168. OUT_CRC_CLEAR_CH0
  169. OUT_CRC_CLEAR_CH1
  170. OUT_CRC_CLEAR_CH1
  171. OUT_CRC_CLEAR_CH2
  172. OUT_CRC_CLEAR_CH2
  173. OUT_CRC_FINAL_RESULT_CH0
  174. OUT_CRC_FINAL_RESULT_CH0
  175. OUT_CRC_FINAL_RESULT_CH1
  176. OUT_CRC_FINAL_RESULT_CH1
  177. OUT_CRC_FINAL_RESULT_CH2
  178. OUT_CRC_FINAL_RESULT_CH2
  179. OUT_CRC_INIT_DATA_CH0
  180. OUT_CRC_INIT_DATA_CH0
  181. OUT_CRC_INIT_DATA_CH1
  182. OUT_CRC_INIT_DATA_CH1
  183. OUT_CRC_INIT_DATA_CH2
  184. OUT_CRC_INIT_DATA_CH2
  185. OUT_DSCR_BF0_CH0
  186. OUT_DSCR_BF0_CH0
  187. OUT_DSCR_BF0_CH1
  188. OUT_DSCR_BF0_CH1
  189. OUT_DSCR_BF0_CH2
  190. OUT_DSCR_BF0_CH2
  191. OUT_DSCR_BF1_CH0
  192. OUT_DSCR_BF1_CH0
  193. OUT_DSCR_BF1_CH1
  194. OUT_DSCR_BF1_CH1
  195. OUT_DSCR_BF1_CH2
  196. OUT_DSCR_BF1_CH2
  197. OUT_DSCR_CH0
  198. OUT_DSCR_CH0
  199. OUT_DSCR_CH1
  200. OUT_DSCR_CH1
  201. OUT_DSCR_CH2
  202. OUT_DSCR_CH2
  203. OUT_EOF_BFR_DES_ADDR_CH0
  204. OUT_EOF_BFR_DES_ADDR_CH0
  205. OUT_EOF_BFR_DES_ADDR_CH1
  206. OUT_EOF_BFR_DES_ADDR_CH1
  207. OUT_EOF_BFR_DES_ADDR_CH2
  208. OUT_EOF_BFR_DES_ADDR_CH2
  209. OUT_EOF_DES_ADDR_CH0
  210. OUT_EOF_DES_ADDR_CH0
  211. OUT_EOF_DES_ADDR_CH1
  212. OUT_EOF_DES_ADDR_CH1
  213. OUT_EOF_DES_ADDR_CH2
  214. OUT_EOF_DES_ADDR_CH2
  215. OUTFIFO_STATUS1_CH0
  216. OUTFIFO_STATUS1_CH0
  217. OUTFIFO_STATUS1_CH1
  218. OUTFIFO_STATUS1_CH1
  219. OUTFIFO_STATUS1_CH2
  220. OUTFIFO_STATUS1_CH2
  221. OUTFIFO_STATUS_CH0
  222. OUTFIFO_STATUS_CH0
  223. OUTFIFO_STATUS_CH1
  224. OUTFIFO_STATUS_CH1
  225. OUTFIFO_STATUS_CH2
  226. OUTFIFO_STATUS_CH2
  227. OUT_INT_CLR_CH0
  228. OUT_INT_CLR_CH0
  229. OUT_INT_CLR_CH1
  230. OUT_INT_CLR_CH1
  231. OUT_INT_CLR_CH2
  232. OUT_INT_CLR_CH2
  233. OUT_INT_ENA_CH0
  234. OUT_INT_ENA_CH0
  235. OUT_INT_ENA_CH1
  236. OUT_INT_ENA_CH1
  237. OUT_INT_ENA_CH2
  238. OUT_INT_ENA_CH2
  239. OUT_INT_RAW_CH0
  240. OUT_INT_RAW_CH0
  241. OUT_INT_RAW_CH1
  242. OUT_INT_RAW_CH1
  243. OUT_INT_RAW_CH2
  244. OUT_INT_RAW_CH2
  245. OUT_INT_ST_CH0
  246. OUT_INT_ST_CH0
  247. OUT_INT_ST_CH1
  248. OUT_INT_ST_CH1
  249. OUT_INT_ST_CH2
  250. OUT_INT_ST_CH2
  251. OUT_LINK1_CH0
  252. OUT_LINK1_CH0
  253. OUT_LINK1_CH1
  254. OUT_LINK1_CH1
  255. OUT_LINK1_CH2
  256. OUT_LINK1_CH2
  257. OUT_LINK2_CH0
  258. OUT_LINK2_CH0
  259. OUT_LINK2_CH1
  260. OUT_LINK2_CH1
  261. OUT_LINK2_CH2
  262. OUT_LINK2_CH2
  263. OUT_PERI_SEL_CH0
  264. OUT_PERI_SEL_CH0
  265. OUT_PERI_SEL_CH1
  266. OUT_PERI_SEL_CH1
  267. OUT_PERI_SEL_CH2
  268. OUT_PERI_SEL_CH2
  269. OUT_PRI_CH0
  270. OUT_PRI_CH0
  271. OUT_PRI_CH1
  272. OUT_PRI_CH1
  273. OUT_PRI_CH2
  274. OUT_PRI_CH2
  275. OUT_PUSH_CH0
  276. OUT_PUSH_CH0
  277. OUT_PUSH_CH1
  278. OUT_PUSH_CH1
  279. OUT_PUSH_CH2
  280. OUT_PUSH_CH2
  281. OUT_RESET_AVAIL_CH0
  282. OUT_RESET_AVAIL_CH0
  283. OUT_RESET_AVAIL_CH1
  284. OUT_RESET_AVAIL_CH1
  285. OUT_RESET_AVAIL_CH2
  286. OUT_RESET_AVAIL_CH2
  287. OUT_STATE_CH0
  288. OUT_STATE_CH0
  289. OUT_STATE_CH1
  290. OUT_STATE_CH1
  291. OUT_STATE_CH2
  292. OUT_STATE_CH2
  293. RDN_ECO_HIGH
  294. RDN_ECO_HIGH
  295. RDN_ECO_LOW
  296. RDN_ECO_LOW
  297. RDN_RESULT
  298. RDN_RESULT
  299. RRESP_CNT
  300. RRESP_CNT
  301. RX_CRC_DATA_EN_ADDR_CH0
  302. RX_CRC_DATA_EN_ADDR_CH0
  303. RX_CRC_DATA_EN_ADDR_CH1
  304. RX_CRC_DATA_EN_ADDR_CH1
  305. RX_CRC_DATA_EN_ADDR_CH2
  306. RX_CRC_DATA_EN_ADDR_CH2
  307. RX_CRC_DATA_EN_WR_DATA_CH0
  308. RX_CRC_DATA_EN_WR_DATA_CH0
  309. RX_CRC_DATA_EN_WR_DATA_CH1
  310. RX_CRC_DATA_EN_WR_DATA_CH1
  311. RX_CRC_DATA_EN_WR_DATA_CH2
  312. RX_CRC_DATA_EN_WR_DATA_CH2
  313. RX_CRC_EN_ADDR_CH0
  314. RX_CRC_EN_ADDR_CH0
  315. RX_CRC_EN_ADDR_CH1
  316. RX_CRC_EN_ADDR_CH1
  317. RX_CRC_EN_ADDR_CH2
  318. RX_CRC_EN_ADDR_CH2
  319. RX_CRC_EN_WR_DATA_CH0
  320. RX_CRC_EN_WR_DATA_CH0
  321. RX_CRC_EN_WR_DATA_CH1
  322. RX_CRC_EN_WR_DATA_CH1
  323. RX_CRC_EN_WR_DATA_CH2
  324. RX_CRC_EN_WR_DATA_CH2
  325. RX_CRC_WIDTH_CH0
  326. RX_CRC_WIDTH_CH0
  327. RX_CRC_WIDTH_CH1
  328. RX_CRC_WIDTH_CH1
  329. RX_CRC_WIDTH_CH2
  330. RX_CRC_WIDTH_CH2
  331. TX_CRC_DATA_EN_ADDR_CH0
  332. TX_CRC_DATA_EN_ADDR_CH0
  333. TX_CRC_DATA_EN_ADDR_CH1
  334. TX_CRC_DATA_EN_ADDR_CH1
  335. TX_CRC_DATA_EN_ADDR_CH2
  336. TX_CRC_DATA_EN_ADDR_CH2
  337. TX_CRC_DATA_EN_WR_DATA_CH0
  338. TX_CRC_DATA_EN_WR_DATA_CH0
  339. TX_CRC_DATA_EN_WR_DATA_CH1
  340. TX_CRC_DATA_EN_WR_DATA_CH1
  341. TX_CRC_DATA_EN_WR_DATA_CH2
  342. TX_CRC_DATA_EN_WR_DATA_CH2
  343. TX_CRC_EN_ADDR_CH0
  344. TX_CRC_EN_ADDR_CH0
  345. TX_CRC_EN_ADDR_CH1
  346. TX_CRC_EN_ADDR_CH1
  347. TX_CRC_EN_ADDR_CH2
  348. TX_CRC_EN_ADDR_CH2
  349. TX_CRC_EN_WR_DATA_CH0
  350. TX_CRC_EN_WR_DATA_CH0
  351. TX_CRC_EN_WR_DATA_CH1
  352. TX_CRC_EN_WR_DATA_CH1
  353. TX_CRC_EN_WR_DATA_CH2
  354. TX_CRC_EN_WR_DATA_CH2
  355. TX_CRC_WIDTH_CH0
  356. TX_CRC_WIDTH_CH0
  357. TX_CRC_WIDTH_CH1
  358. TX_CRC_WIDTH_CH1
  359. TX_CRC_WIDTH_CH2
  360. TX_CRC_WIDTH_CH2
  361. WEIGHT_EN
  362. WEIGHT_EN
  363. WRESP_CNT
  364. WRESP_CNT