Browse Registers In Our Database

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Registers in Espressif Systems /ESP32-P4 /CACHE

  1. CLOCK_GATE
  2. CLOCK_GATE
  3. DATE
  4. DATE
  5. L1_BYPASS_CACHE_CONF
  6. L1_BYPASS_CACHE_CONF
  7. L1_CACHE_ACS_CNT_CTRL
  8. L1_CACHE_ACS_CNT_CTRL
  9. L1_CACHE_ACS_CNT_INT_CLR
  10. L1_CACHE_ACS_CNT_INT_CLR
  11. L1_CACHE_ACS_CNT_INT_ENA
  12. L1_CACHE_ACS_CNT_INT_ENA
  13. L1_CACHE_ACS_CNT_INT_RAW
  14. L1_CACHE_ACS_CNT_INT_RAW
  15. L1_CACHE_ACS_CNT_INT_ST
  16. L1_CACHE_ACS_CNT_INT_ST
  17. L1_CACHE_ACS_FAIL_CTRL
  18. L1_CACHE_ACS_FAIL_CTRL
  19. L1_CACHE_ACS_FAIL_INT_CLR
  20. L1_CACHE_ACS_FAIL_INT_CLR
  21. L1_CACHE_ACS_FAIL_INT_ENA
  22. L1_CACHE_ACS_FAIL_INT_ENA
  23. L1_CACHE_ACS_FAIL_INT_RAW
  24. L1_CACHE_ACS_FAIL_INT_RAW
  25. L1_CACHE_ACS_FAIL_INT_ST
  26. L1_CACHE_ACS_FAIL_INT_ST
  27. L1_CACHE_ATOMIC_CONF
  28. L1_CACHE_ATOMIC_CONF
  29. L1_CACHE_AUTOLOAD_BUF_CLR_CTRL
  30. L1_CACHE_AUTOLOAD_BUF_CLR_CTRL
  31. L1_CACHE_DATA_MEM_ACS_CONF
  32. L1_CACHE_DATA_MEM_ACS_CONF
  33. L1_CACHE_DATA_MEM_POWER_CTRL
  34. L1_CACHE_DATA_MEM_POWER_CTRL
  35. L1_CACHE_DEBUG_BUS
  36. L1_CACHE_DEBUG_BUS
  37. L1_CACHE_FREEZE_CTRL
  38. L1_CACHE_FREEZE_CTRL
  39. L1_CACHE_OBJECT_CTRL
  40. L1_CACHE_OBJECT_CTRL
  41. L1_CACHE_PRELOAD_RST_CTRL
  42. L1_CACHE_PRELOAD_RST_CTRL
  43. L1_CACHE_SYNC_RST_CTRL
  44. L1_CACHE_SYNC_RST_CTRL
  45. L1_CACHE_TAG_MEM_ACS_CONF
  46. L1_CACHE_TAG_MEM_ACS_CONF
  47. L1_CACHE_TAG_MEM_POWER_CTRL
  48. L1_CACHE_TAG_MEM_POWER_CTRL
  49. L1_CACHE_VADDR
  50. L1_CACHE_VADDR
  51. L1_CACHE_WAY_OBJECT
  52. L1_CACHE_WAY_OBJECT
  53. L1_CACHE_WRAP_AROUND_CTRL
  54. L1_CACHE_WRAP_AROUND_CTRL
  55. L1_DBUS0_ACS_CONFLICT_CNT
  56. L1_DBUS0_ACS_CONFLICT_CNT
  57. L1_DBUS0_ACS_HIT_CNT
  58. L1_DBUS0_ACS_HIT_CNT
  59. L1_DBUS0_ACS_MISS_CNT
  60. L1_DBUS0_ACS_MISS_CNT
  61. L1_DBUS0_ACS_NXTLVL_RD_CNT
  62. L1_DBUS0_ACS_NXTLVL_RD_CNT
  63. L1_DBUS0_ACS_NXTLVL_WR_CNT
  64. L1_DBUS0_ACS_NXTLVL_WR_CNT
  65. L1_DBUS1_ACS_CONFLICT_CNT
  66. L1_DBUS1_ACS_CONFLICT_CNT
  67. L1_DBUS1_ACS_HIT_CNT
  68. L1_DBUS1_ACS_HIT_CNT
  69. L1_DBUS1_ACS_MISS_CNT
  70. L1_DBUS1_ACS_MISS_CNT
  71. L1_DBUS1_ACS_NXTLVL_RD_CNT
  72. L1_DBUS1_ACS_NXTLVL_RD_CNT
  73. L1_DBUS1_ACS_NXTLVL_WR_CNT
  74. L1_DBUS1_ACS_NXTLVL_WR_CNT
  75. L1_DBUS2_ACS_CONFLICT_CNT
  76. L1_DBUS2_ACS_CONFLICT_CNT
  77. L1_DBUS2_ACS_HIT_CNT
  78. L1_DBUS2_ACS_HIT_CNT
  79. L1_DBUS2_ACS_MISS_CNT
  80. L1_DBUS2_ACS_MISS_CNT
  81. L1_DBUS2_ACS_NXTLVL_RD_CNT
  82. L1_DBUS2_ACS_NXTLVL_RD_CNT
  83. L1_DBUS2_ACS_NXTLVL_WR_CNT
  84. L1_DBUS2_ACS_NXTLVL_WR_CNT
  85. L1_DBUS3_ACS_CONFLICT_CNT
  86. L1_DBUS3_ACS_CONFLICT_CNT
  87. L1_DBUS3_ACS_HIT_CNT
  88. L1_DBUS3_ACS_HIT_CNT
  89. L1_DBUS3_ACS_MISS_CNT
  90. L1_DBUS3_ACS_MISS_CNT
  91. L1_DBUS3_ACS_NXTLVL_RD_CNT
  92. L1_DBUS3_ACS_NXTLVL_RD_CNT
  93. L1_DBUS3_ACS_NXTLVL_WR_CNT
  94. L1_DBUS3_ACS_NXTLVL_WR_CNT
  95. L1_DCACHE_ACS_FAIL_ADDR
  96. L1_DCACHE_ACS_FAIL_ADDR
  97. L1_DCACHE_ACS_FAIL_ID_ATTR
  98. L1_DCACHE_ACS_FAIL_ID_ATTR
  99. L1_DCACHE_AUTOLOAD_CTRL
  100. L1_DCACHE_AUTOLOAD_CTRL
  101. L1_DCACHE_AUTOLOAD_SCT0_ADDR
  102. L1_DCACHE_AUTOLOAD_SCT0_ADDR
  103. L1_DCACHE_AUTOLOAD_SCT0_SIZE
  104. L1_DCACHE_AUTOLOAD_SCT0_SIZE
  105. L1_DCACHE_AUTOLOAD_SCT1_ADDR
  106. L1_DCACHE_AUTOLOAD_SCT1_ADDR
  107. L1_DCACHE_AUTOLOAD_SCT1_SIZE
  108. L1_DCACHE_AUTOLOAD_SCT1_SIZE
  109. L1_DCACHE_AUTOLOAD_SCT2_ADDR
  110. L1_DCACHE_AUTOLOAD_SCT2_ADDR
  111. L1_DCACHE_AUTOLOAD_SCT2_SIZE
  112. L1_DCACHE_AUTOLOAD_SCT2_SIZE
  113. L1_DCACHE_AUTOLOAD_SCT3_ADDR
  114. L1_DCACHE_AUTOLOAD_SCT3_ADDR
  115. L1_DCACHE_AUTOLOAD_SCT3_SIZE
  116. L1_DCACHE_AUTOLOAD_SCT3_SIZE
  117. L1_DCACHE_BLOCKSIZE_CONF
  118. L1_DCACHE_BLOCKSIZE_CONF
  119. L1_DCACHE_CACHESIZE_CONF
  120. L1_DCACHE_CACHESIZE_CONF
  121. L1_DCACHE_CTRL
  122. L1_DCACHE_CTRL
  123. L1_DCACHE_PRELOAD_ADDR
  124. L1_DCACHE_PRELOAD_ADDR
  125. L1_DCACHE_PRELOAD_CTRL
  126. L1_DCACHE_PRELOAD_CTRL
  127. L1_DCACHE_PRELOAD_SIZE
  128. L1_DCACHE_PRELOAD_SIZE
  129. L1_DCACHE_PRELOCK_CONF
  130. L1_DCACHE_PRELOCK_CONF
  131. L1_DCACHE_PRELOCK_SCT0_ADDR
  132. L1_DCACHE_PRELOCK_SCT0_ADDR
  133. L1_DCACHE_PRELOCK_SCT1_ADDR
  134. L1_DCACHE_PRELOCK_SCT1_ADDR
  135. L1_DCACHE_PRELOCK_SCT_SIZE
  136. L1_DCACHE_PRELOCK_SCT_SIZE
  137. L1_IBUS0_ACS_CONFLICT_CNT
  138. L1_IBUS0_ACS_CONFLICT_CNT
  139. L1_IBUS0_ACS_HIT_CNT
  140. L1_IBUS0_ACS_HIT_CNT
  141. L1_IBUS0_ACS_MISS_CNT
  142. L1_IBUS0_ACS_MISS_CNT
  143. L1_IBUS0_ACS_NXTLVL_RD_CNT
  144. L1_IBUS0_ACS_NXTLVL_RD_CNT
  145. L1_IBUS1_ACS_CONFLICT_CNT
  146. L1_IBUS1_ACS_CONFLICT_CNT
  147. L1_IBUS1_ACS_HIT_CNT
  148. L1_IBUS1_ACS_HIT_CNT
  149. L1_IBUS1_ACS_MISS_CNT
  150. L1_IBUS1_ACS_MISS_CNT
  151. L1_IBUS1_ACS_NXTLVL_RD_CNT
  152. L1_IBUS1_ACS_NXTLVL_RD_CNT
  153. L1_IBUS2_ACS_CONFLICT_CNT
  154. L1_IBUS2_ACS_CONFLICT_CNT
  155. L1_IBUS2_ACS_HIT_CNT
  156. L1_IBUS2_ACS_HIT_CNT
  157. L1_IBUS2_ACS_MISS_CNT
  158. L1_IBUS2_ACS_MISS_CNT
  159. L1_IBUS2_ACS_NXTLVL_RD_CNT
  160. L1_IBUS2_ACS_NXTLVL_RD_CNT
  161. L1_IBUS3_ACS_CONFLICT_CNT
  162. L1_IBUS3_ACS_CONFLICT_CNT
  163. L1_IBUS3_ACS_HIT_CNT
  164. L1_IBUS3_ACS_HIT_CNT
  165. L1_IBUS3_ACS_MISS_CNT
  166. L1_IBUS3_ACS_MISS_CNT
  167. L1_IBUS3_ACS_NXTLVL_RD_CNT
  168. L1_IBUS3_ACS_NXTLVL_RD_CNT
  169. L1_ICACHE0_ACS_FAIL_ADDR
  170. L1_ICACHE0_ACS_FAIL_ADDR
  171. L1_ICACHE0_ACS_FAIL_ID_ATTR
  172. L1_ICACHE0_ACS_FAIL_ID_ATTR
  173. L1_ICACHE0_AUTOLOAD_CTRL
  174. L1_ICACHE0_AUTOLOAD_CTRL
  175. L1_ICACHE0_AUTOLOAD_SCT0_ADDR
  176. L1_ICACHE0_AUTOLOAD_SCT0_ADDR
  177. L1_ICACHE0_AUTOLOAD_SCT0_SIZE
  178. L1_ICACHE0_AUTOLOAD_SCT0_SIZE
  179. L1_ICACHE0_AUTOLOAD_SCT1_ADDR
  180. L1_ICACHE0_AUTOLOAD_SCT1_ADDR
  181. L1_ICACHE0_AUTOLOAD_SCT1_SIZE
  182. L1_ICACHE0_AUTOLOAD_SCT1_SIZE
  183. L1_ICACHE0_PRELOAD_ADDR
  184. L1_ICACHE0_PRELOAD_ADDR
  185. L1_ICACHE0_PRELOAD_CTRL
  186. L1_ICACHE0_PRELOAD_CTRL
  187. L1_ICACHE0_PRELOAD_SIZE
  188. L1_ICACHE0_PRELOAD_SIZE
  189. L1_ICACHE0_PRELOCK_CONF
  190. L1_ICACHE0_PRELOCK_CONF
  191. L1_ICACHE0_PRELOCK_SCT0_ADDR
  192. L1_ICACHE0_PRELOCK_SCT0_ADDR
  193. L1_ICACHE0_PRELOCK_SCT1_ADDR
  194. L1_ICACHE0_PRELOCK_SCT1_ADDR
  195. L1_ICACHE0_PRELOCK_SCT_SIZE
  196. L1_ICACHE0_PRELOCK_SCT_SIZE
  197. L1_ICACHE1_ACS_FAIL_ADDR
  198. L1_ICACHE1_ACS_FAIL_ADDR
  199. L1_ICACHE1_ACS_FAIL_ID_ATTR
  200. L1_ICACHE1_ACS_FAIL_ID_ATTR
  201. L1_ICACHE1_AUTOLOAD_CTRL
  202. L1_ICACHE1_AUTOLOAD_CTRL
  203. L1_ICACHE1_AUTOLOAD_SCT0_ADDR
  204. L1_ICACHE1_AUTOLOAD_SCT0_ADDR
  205. L1_ICACHE1_AUTOLOAD_SCT0_SIZE
  206. L1_ICACHE1_AUTOLOAD_SCT0_SIZE
  207. L1_ICACHE1_AUTOLOAD_SCT1_ADDR
  208. L1_ICACHE1_AUTOLOAD_SCT1_ADDR
  209. L1_ICACHE1_AUTOLOAD_SCT1_SIZE
  210. L1_ICACHE1_AUTOLOAD_SCT1_SIZE
  211. L1_ICACHE1_PRELOAD_ADDR
  212. L1_ICACHE1_PRELOAD_ADDR
  213. L1_ICACHE1_PRELOAD_CTRL
  214. L1_ICACHE1_PRELOAD_CTRL
  215. L1_ICACHE1_PRELOAD_SIZE
  216. L1_ICACHE1_PRELOAD_SIZE
  217. L1_ICACHE1_PRELOCK_CONF
  218. L1_ICACHE1_PRELOCK_CONF
  219. L1_ICACHE1_PRELOCK_SCT0_ADDR
  220. L1_ICACHE1_PRELOCK_SCT0_ADDR
  221. L1_ICACHE1_PRELOCK_SCT1_ADDR
  222. L1_ICACHE1_PRELOCK_SCT1_ADDR
  223. L1_ICACHE1_PRELOCK_SCT_SIZE
  224. L1_ICACHE1_PRELOCK_SCT_SIZE
  225. L1_ICACHE2_ACS_FAIL_ADDR
  226. L1_ICACHE2_ACS_FAIL_ADDR
  227. L1_ICACHE2_ACS_FAIL_ID_ATTR
  228. L1_ICACHE2_ACS_FAIL_ID_ATTR
  229. L1_ICACHE2_AUTOLOAD_CTRL
  230. L1_ICACHE2_AUTOLOAD_CTRL
  231. L1_ICACHE2_AUTOLOAD_SCT0_ADDR
  232. L1_ICACHE2_AUTOLOAD_SCT0_ADDR
  233. L1_ICACHE2_AUTOLOAD_SCT0_SIZE
  234. L1_ICACHE2_AUTOLOAD_SCT0_SIZE
  235. L1_ICACHE2_AUTOLOAD_SCT1_ADDR
  236. L1_ICACHE2_AUTOLOAD_SCT1_ADDR
  237. L1_ICACHE2_AUTOLOAD_SCT1_SIZE
  238. L1_ICACHE2_AUTOLOAD_SCT1_SIZE
  239. L1_ICACHE2_PRELOAD_ADDR
  240. L1_ICACHE2_PRELOAD_ADDR
  241. L1_ICACHE2_PRELOAD_CTRL
  242. L1_ICACHE2_PRELOAD_CTRL
  243. L1_ICACHE2_PRELOAD_SIZE
  244. L1_ICACHE2_PRELOAD_SIZE
  245. L1_ICACHE2_PRELOCK_CONF
  246. L1_ICACHE2_PRELOCK_CONF
  247. L1_ICACHE2_PRELOCK_SCT0_ADDR
  248. L1_ICACHE2_PRELOCK_SCT0_ADDR
  249. L1_ICACHE2_PRELOCK_SCT1_ADDR
  250. L1_ICACHE2_PRELOCK_SCT1_ADDR
  251. L1_ICACHE2_PRELOCK_SCT_SIZE
  252. L1_ICACHE2_PRELOCK_SCT_SIZE
  253. L1_ICACHE3_ACS_FAIL_ADDR
  254. L1_ICACHE3_ACS_FAIL_ADDR
  255. L1_ICACHE3_ACS_FAIL_ID_ATTR
  256. L1_ICACHE3_ACS_FAIL_ID_ATTR
  257. L1_ICACHE3_AUTOLOAD_CTRL
  258. L1_ICACHE3_AUTOLOAD_CTRL
  259. L1_ICACHE3_AUTOLOAD_SCT0_ADDR
  260. L1_ICACHE3_AUTOLOAD_SCT0_ADDR
  261. L1_ICACHE3_AUTOLOAD_SCT0_SIZE
  262. L1_ICACHE3_AUTOLOAD_SCT0_SIZE
  263. L1_ICACHE3_AUTOLOAD_SCT1_ADDR
  264. L1_ICACHE3_AUTOLOAD_SCT1_ADDR
  265. L1_ICACHE3_AUTOLOAD_SCT1_SIZE
  266. L1_ICACHE3_AUTOLOAD_SCT1_SIZE
  267. L1_ICACHE3_PRELOAD_ADDR
  268. L1_ICACHE3_PRELOAD_ADDR
  269. L1_ICACHE3_PRELOAD_CTRL
  270. L1_ICACHE3_PRELOAD_CTRL
  271. L1_ICACHE3_PRELOAD_SIZE
  272. L1_ICACHE3_PRELOAD_SIZE
  273. L1_ICACHE3_PRELOCK_CONF
  274. L1_ICACHE3_PRELOCK_CONF
  275. L1_ICACHE3_PRELOCK_SCT0_ADDR
  276. L1_ICACHE3_PRELOCK_SCT0_ADDR
  277. L1_ICACHE3_PRELOCK_SCT1_ADDR
  278. L1_ICACHE3_PRELOCK_SCT1_ADDR
  279. L1_ICACHE3_PRELOCK_SCT_SIZE
  280. L1_ICACHE3_PRELOCK_SCT_SIZE
  281. L1_ICACHE_BLOCKSIZE_CONF
  282. L1_ICACHE_BLOCKSIZE_CONF
  283. L1_ICACHE_CACHESIZE_CONF
  284. L1_ICACHE_CACHESIZE_CONF
  285. L1_ICACHE_CTRL
  286. L1_ICACHE_CTRL
  287. L1_UNALLOCATE_BUFFER_CLEAR
  288. L1_UNALLOCATE_BUFFER_CLEAR
  289. L2_BYPASS_CACHE_CONF
  290. L2_BYPASS_CACHE_CONF
  291. L2_CACHE_ACCESS_ATTR_CTRL
  292. L2_CACHE_ACCESS_ATTR_CTRL
  293. L2_CACHE_ACS_CNT_CTRL
  294. L2_CACHE_ACS_CNT_CTRL
  295. L2_CACHE_ACS_CNT_INT_CLR
  296. L2_CACHE_ACS_CNT_INT_CLR
  297. L2_CACHE_ACS_CNT_INT_ENA
  298. L2_CACHE_ACS_CNT_INT_ENA
  299. L2_CACHE_ACS_CNT_INT_RAW
  300. L2_CACHE_ACS_CNT_INT_RAW
  301. L2_CACHE_ACS_CNT_INT_ST
  302. L2_CACHE_ACS_CNT_INT_ST
  303. L2_CACHE_ACS_FAIL_ADDR
  304. L2_CACHE_ACS_FAIL_ADDR
  305. L2_CACHE_ACS_FAIL_CTRL
  306. L2_CACHE_ACS_FAIL_CTRL
  307. L2_CACHE_ACS_FAIL_ID_ATTR
  308. L2_CACHE_ACS_FAIL_ID_ATTR
  309. L2_CACHE_ACS_FAIL_INT_CLR
  310. L2_CACHE_ACS_FAIL_INT_CLR
  311. L2_CACHE_ACS_FAIL_INT_ENA
  312. L2_CACHE_ACS_FAIL_INT_ENA
  313. L2_CACHE_ACS_FAIL_INT_RAW
  314. L2_CACHE_ACS_FAIL_INT_RAW
  315. L2_CACHE_ACS_FAIL_INT_ST
  316. L2_CACHE_ACS_FAIL_INT_ST
  317. L2_CACHE_AUTOLOAD_BUF_CLR_CTRL
  318. L2_CACHE_AUTOLOAD_BUF_CLR_CTRL
  319. L2_CACHE_AUTOLOAD_CTRL
  320. L2_CACHE_AUTOLOAD_CTRL
  321. L2_CACHE_AUTOLOAD_SCT0_ADDR
  322. L2_CACHE_AUTOLOAD_SCT0_ADDR
  323. L2_CACHE_AUTOLOAD_SCT0_SIZE
  324. L2_CACHE_AUTOLOAD_SCT0_SIZE
  325. L2_CACHE_AUTOLOAD_SCT1_ADDR
  326. L2_CACHE_AUTOLOAD_SCT1_ADDR
  327. L2_CACHE_AUTOLOAD_SCT1_SIZE
  328. L2_CACHE_AUTOLOAD_SCT1_SIZE
  329. L2_CACHE_AUTOLOAD_SCT2_ADDR
  330. L2_CACHE_AUTOLOAD_SCT2_ADDR
  331. L2_CACHE_AUTOLOAD_SCT2_SIZE
  332. L2_CACHE_AUTOLOAD_SCT2_SIZE
  333. L2_CACHE_AUTOLOAD_SCT3_ADDR
  334. L2_CACHE_AUTOLOAD_SCT3_ADDR
  335. L2_CACHE_AUTOLOAD_SCT3_SIZE
  336. L2_CACHE_AUTOLOAD_SCT3_SIZE
  337. L2_CACHE_BLOCKSIZE_CONF
  338. L2_CACHE_BLOCKSIZE_CONF
  339. L2_CACHE_CACHESIZE_CONF
  340. L2_CACHE_CACHESIZE_CONF
  341. L2_CACHE_CTRL
  342. L2_CACHE_CTRL
  343. L2_CACHE_DATA_MEM_ACS_CONF
  344. L2_CACHE_DATA_MEM_ACS_CONF
  345. L2_CACHE_DATA_MEM_POWER_CTRL
  346. L2_CACHE_DATA_MEM_POWER_CTRL
  347. L2_CACHE_DEBUG_BUS
  348. L2_CACHE_DEBUG_BUS
  349. L2_CACHE_FREEZE_CTRL
  350. L2_CACHE_FREEZE_CTRL
  351. L2_CACHE_OBJECT_CTRL
  352. L2_CACHE_OBJECT_CTRL
  353. L2_CACHE_PRELOAD_ADDR
  354. L2_CACHE_PRELOAD_ADDR
  355. L2_CACHE_PRELOAD_CTRL
  356. L2_CACHE_PRELOAD_CTRL
  357. L2_CACHE_PRELOAD_RST_CTRL
  358. L2_CACHE_PRELOAD_RST_CTRL
  359. L2_CACHE_PRELOAD_SIZE
  360. L2_CACHE_PRELOAD_SIZE
  361. L2_CACHE_PRELOCK_CONF
  362. L2_CACHE_PRELOCK_CONF
  363. L2_CACHE_PRELOCK_SCT0_ADDR
  364. L2_CACHE_PRELOCK_SCT0_ADDR
  365. L2_CACHE_PRELOCK_SCT1_ADDR
  366. L2_CACHE_PRELOCK_SCT1_ADDR
  367. L2_CACHE_PRELOCK_SCT_SIZE
  368. L2_CACHE_PRELOCK_SCT_SIZE
  369. L2_CACHE_SYNC_PRELOAD_EXCEPTION
  370. L2_CACHE_SYNC_PRELOAD_EXCEPTION
  371. L2_CACHE_SYNC_PRELOAD_INT_CLR
  372. L2_CACHE_SYNC_PRELOAD_INT_CLR
  373. L2_CACHE_SYNC_PRELOAD_INT_ENA
  374. L2_CACHE_SYNC_PRELOAD_INT_ENA
  375. L2_CACHE_SYNC_PRELOAD_INT_RAW
  376. L2_CACHE_SYNC_PRELOAD_INT_RAW
  377. L2_CACHE_SYNC_PRELOAD_INT_ST
  378. L2_CACHE_SYNC_PRELOAD_INT_ST
  379. L2_CACHE_SYNC_RST_CTRL
  380. L2_CACHE_SYNC_RST_CTRL
  381. L2_CACHE_TAG_MEM_ACS_CONF
  382. L2_CACHE_TAG_MEM_ACS_CONF
  383. L2_CACHE_TAG_MEM_POWER_CTRL
  384. L2_CACHE_TAG_MEM_POWER_CTRL
  385. L2_CACHE_VADDR
  386. L2_CACHE_VADDR
  387. L2_CACHE_WAY_OBJECT
  388. L2_CACHE_WAY_OBJECT
  389. L2_CACHE_WRAP_AROUND_CTRL
  390. L2_CACHE_WRAP_AROUND_CTRL
  391. L2_DBUS0_ACS_CONFLICT_CNT
  392. L2_DBUS0_ACS_CONFLICT_CNT
  393. L2_DBUS0_ACS_HIT_CNT
  394. L2_DBUS0_ACS_HIT_CNT
  395. L2_DBUS0_ACS_MISS_CNT
  396. L2_DBUS0_ACS_MISS_CNT
  397. L2_DBUS0_ACS_NXTLVL_RD_CNT
  398. L2_DBUS0_ACS_NXTLVL_RD_CNT
  399. L2_DBUS0_ACS_NXTLVL_WR_CNT
  400. L2_DBUS0_ACS_NXTLVL_WR_CNT
  401. L2_DBUS1_ACS_CONFLICT_CNT
  402. L2_DBUS1_ACS_CONFLICT_CNT
  403. L2_DBUS1_ACS_HIT_CNT
  404. L2_DBUS1_ACS_HIT_CNT
  405. L2_DBUS1_ACS_MISS_CNT
  406. L2_DBUS1_ACS_MISS_CNT
  407. L2_DBUS1_ACS_NXTLVL_RD_CNT
  408. L2_DBUS1_ACS_NXTLVL_RD_CNT
  409. L2_DBUS1_ACS_NXTLVL_WR_CNT
  410. L2_DBUS1_ACS_NXTLVL_WR_CNT
  411. L2_DBUS2_ACS_CONFLICT_CNT
  412. L2_DBUS2_ACS_CONFLICT_CNT
  413. L2_DBUS2_ACS_HIT_CNT
  414. L2_DBUS2_ACS_HIT_CNT
  415. L2_DBUS2_ACS_MISS_CNT
  416. L2_DBUS2_ACS_MISS_CNT
  417. L2_DBUS2_ACS_NXTLVL_RD_CNT
  418. L2_DBUS2_ACS_NXTLVL_RD_CNT
  419. L2_DBUS2_ACS_NXTLVL_WR_CNT
  420. L2_DBUS2_ACS_NXTLVL_WR_CNT
  421. L2_DBUS3_ACS_CONFLICT_CNT
  422. L2_DBUS3_ACS_CONFLICT_CNT
  423. L2_DBUS3_ACS_HIT_CNT
  424. L2_DBUS3_ACS_HIT_CNT
  425. L2_DBUS3_ACS_MISS_CNT
  426. L2_DBUS3_ACS_MISS_CNT
  427. L2_DBUS3_ACS_NXTLVL_RD_CNT
  428. L2_DBUS3_ACS_NXTLVL_RD_CNT
  429. L2_DBUS3_ACS_NXTLVL_WR_CNT
  430. L2_DBUS3_ACS_NXTLVL_WR_CNT
  431. L2_IBUS0_ACS_CONFLICT_CNT
  432. L2_IBUS0_ACS_CONFLICT_CNT
  433. L2_IBUS0_ACS_HIT_CNT
  434. L2_IBUS0_ACS_HIT_CNT
  435. L2_IBUS0_ACS_MISS_CNT
  436. L2_IBUS0_ACS_MISS_CNT
  437. L2_IBUS0_ACS_NXTLVL_RD_CNT
  438. L2_IBUS0_ACS_NXTLVL_RD_CNT
  439. L2_IBUS1_ACS_CONFLICT_CNT
  440. L2_IBUS1_ACS_CONFLICT_CNT
  441. L2_IBUS1_ACS_HIT_CNT
  442. L2_IBUS1_ACS_HIT_CNT
  443. L2_IBUS1_ACS_MISS_CNT
  444. L2_IBUS1_ACS_MISS_CNT
  445. L2_IBUS1_ACS_NXTLVL_RD_CNT
  446. L2_IBUS1_ACS_NXTLVL_RD_CNT
  447. L2_IBUS2_ACS_CONFLICT_CNT
  448. L2_IBUS2_ACS_CONFLICT_CNT
  449. L2_IBUS2_ACS_HIT_CNT
  450. L2_IBUS2_ACS_HIT_CNT
  451. L2_IBUS2_ACS_MISS_CNT
  452. L2_IBUS2_ACS_MISS_CNT
  453. L2_IBUS2_ACS_NXTLVL_RD_CNT
  454. L2_IBUS2_ACS_NXTLVL_RD_CNT
  455. L2_IBUS3_ACS_CONFLICT_CNT
  456. L2_IBUS3_ACS_CONFLICT_CNT
  457. L2_IBUS3_ACS_HIT_CNT
  458. L2_IBUS3_ACS_HIT_CNT
  459. L2_IBUS3_ACS_MISS_CNT
  460. L2_IBUS3_ACS_MISS_CNT
  461. L2_IBUS3_ACS_NXTLVL_RD_CNT
  462. L2_IBUS3_ACS_NXTLVL_RD_CNT
  463. L2_UNALLOCATE_BUFFER_CLEAR
  464. L2_UNALLOCATE_BUFFER_CLEAR
  465. LEVEL_SPLIT0
  466. LEVEL_SPLIT0
  467. LEVEL_SPLIT1
  468. LEVEL_SPLIT1
  469. LOCK_ADDR
  470. LOCK_ADDR
  471. LOCK_CTRL
  472. LOCK_CTRL
  473. LOCK_MAP
  474. LOCK_MAP
  475. LOCK_SIZE
  476. LOCK_SIZE
  477. REDUNDANCY_SIG0
  478. REDUNDANCY_SIG0
  479. REDUNDANCY_SIG1
  480. REDUNDANCY_SIG1
  481. REDUNDANCY_SIG2
  482. REDUNDANCY_SIG2
  483. REDUNDANCY_SIG3
  484. REDUNDANCY_SIG3
  485. REDUNDANCY_SIG4
  486. REDUNDANCY_SIG4
  487. SYNC_ADDR
  488. SYNC_ADDR
  489. SYNC_CTRL
  490. SYNC_CTRL
  491. SYNC_L1_CACHE_PRELOAD_EXCEPTION
  492. SYNC_L1_CACHE_PRELOAD_EXCEPTION
  493. SYNC_L1_CACHE_PRELOAD_INT_CLR
  494. SYNC_L1_CACHE_PRELOAD_INT_CLR
  495. SYNC_L1_CACHE_PRELOAD_INT_ENA
  496. SYNC_L1_CACHE_PRELOAD_INT_ENA
  497. SYNC_L1_CACHE_PRELOAD_INT_RAW
  498. SYNC_L1_CACHE_PRELOAD_INT_RAW
  499. SYNC_L1_CACHE_PRELOAD_INT_ST
  500. SYNC_L1_CACHE_PRELOAD_INT_ST
  501. SYNC_MAP
  502. SYNC_MAP
  503. SYNC_SIZE
  504. SYNC_SIZE