Browse Registers In Our Database

Browse below to find the registers you are looking for, or search for one. For each register you can visualize its contents, and for many there is some basic reference information.

Registers in Espressif Systems /ESP32-P4 /DMA

  1. CFG0
  2. CFG0
  3. CH1_AXI_ID0
  4. CH1_AXI_ID0
  5. CH1_AXI_QOS0
  6. CH1_AXI_QOS0
  7. CH1_BLK_TFR_RESUMEREQ0
  8. CH1_BLK_TFR_RESUMEREQ0
  9. CH1_BLOCK_TS0
  10. CH1_BLOCK_TS0
  11. CH1_CFG0
  12. CH1_CFG0
  13. CH1_CFG1
  14. CH1_CFG1
  15. CH1_CTL0
  16. CH1_CTL0
  17. CH1_CTL1
  18. CH1_CTL1
  19. CH1_DAR0
  20. CH1_DAR0
  21. CH1_DAR1
  22. CH1_DAR1
  23. CH1_DSTAT0
  24. CH1_DSTAT0
  25. CH1_DSTATAR0
  26. CH1_DSTATAR0
  27. CH1_DSTATAR1
  28. CH1_DSTATAR1
  29. CH1_INTCLEAR0
  30. CH1_INTCLEAR0
  31. CH1_INTCLEAR1
  32. CH1_INTCLEAR1
  33. CH1_INTSIGNAL_ENABLE0
  34. CH1_INTSIGNAL_ENABLE0
  35. CH1_INTSIGNAL_ENABLE1
  36. CH1_INTSIGNAL_ENABLE1
  37. CH1_INTSTATUS0
  38. CH1_INTSTATUS0
  39. CH1_INTSTATUS1
  40. CH1_INTSTATUS1
  41. CH1_INTSTATUS_ENABLE0
  42. CH1_INTSTATUS_ENABLE0
  43. CH1_INTSTATUS_ENABLE1
  44. CH1_INTSTATUS_ENABLE1
  45. CH1_LLP0
  46. CH1_LLP0
  47. CH1_LLP1
  48. CH1_LLP1
  49. CH1_SAR0
  50. CH1_SAR0
  51. CH1_SAR1
  52. CH1_SAR1
  53. CH1_SSTAT0
  54. CH1_SSTAT0
  55. CH1_SSTATAR0
  56. CH1_SSTATAR0
  57. CH1_SSTATAR1
  58. CH1_SSTATAR1
  59. CH1_STATUS0
  60. CH1_STATUS0
  61. CH1_STATUS1
  62. CH1_STATUS1
  63. CH1_SWHSDST0
  64. CH1_SWHSDST0
  65. CH1_SWHSSRC0
  66. CH1_SWHSSRC0
  67. CH2_AXI_ID0
  68. CH2_AXI_ID0
  69. CH2_AXI_QOS0
  70. CH2_AXI_QOS0
  71. CH2_BLK_TFR_RESUMEREQ0
  72. CH2_BLK_TFR_RESUMEREQ0
  73. CH2_BLOCK_TS0
  74. CH2_BLOCK_TS0
  75. CH2_CFG0
  76. CH2_CFG0
  77. CH2_CFG1
  78. CH2_CFG1
  79. CH2_CTL0
  80. CH2_CTL0
  81. CH2_CTL1
  82. CH2_CTL1
  83. CH2_DAR0
  84. CH2_DAR0
  85. CH2_DAR1
  86. CH2_DAR1
  87. CH2_DSTAT0
  88. CH2_DSTAT0
  89. CH2_DSTATAR0
  90. CH2_DSTATAR0
  91. CH2_DSTATAR1
  92. CH2_DSTATAR1
  93. CH2_INTCLEAR0
  94. CH2_INTCLEAR0
  95. CH2_INTCLEAR1
  96. CH2_INTCLEAR1
  97. CH2_INTSIGNAL_ENABLE0
  98. CH2_INTSIGNAL_ENABLE0
  99. CH2_INTSIGNAL_ENABLE1
  100. CH2_INTSIGNAL_ENABLE1
  101. CH2_INTSTATUS0
  102. CH2_INTSTATUS0
  103. CH2_INTSTATUS1
  104. CH2_INTSTATUS1
  105. CH2_INTSTATUS_ENABLE0
  106. CH2_INTSTATUS_ENABLE0
  107. CH2_INTSTATUS_ENABLE1
  108. CH2_INTSTATUS_ENABLE1
  109. CH2_LLP0
  110. CH2_LLP0
  111. CH2_LLP1
  112. CH2_LLP1
  113. CH2_SAR0
  114. CH2_SAR0
  115. CH2_SAR1
  116. CH2_SAR1
  117. CH2_SSTAT0
  118. CH2_SSTAT0
  119. CH2_SSTATAR0
  120. CH2_SSTATAR0
  121. CH2_SSTATAR1
  122. CH2_SSTATAR1
  123. CH2_STATUS0
  124. CH2_STATUS0
  125. CH2_STATUS1
  126. CH2_STATUS1
  127. CH2_SWHSDST0
  128. CH2_SWHSDST0
  129. CH2_SWHSSRC0
  130. CH2_SWHSSRC0
  131. CH3_AXI_ID0
  132. CH3_AXI_ID0
  133. CH3_AXI_QOS0
  134. CH3_AXI_QOS0
  135. CH3_BLK_TFR_RESUMEREQ0
  136. CH3_BLK_TFR_RESUMEREQ0
  137. CH3_BLOCK_TS0
  138. CH3_BLOCK_TS0
  139. CH3_CFG0
  140. CH3_CFG0
  141. CH3_CFG1
  142. CH3_CFG1
  143. CH3_CTL0
  144. CH3_CTL0
  145. CH3_CTL1
  146. CH3_CTL1
  147. CH3_DAR0
  148. CH3_DAR0
  149. CH3_DAR1
  150. CH3_DAR1
  151. CH3_DSTAT0
  152. CH3_DSTAT0
  153. CH3_DSTATAR0
  154. CH3_DSTATAR0
  155. CH3_DSTATAR1
  156. CH3_DSTATAR1
  157. CH3_INTCLEAR0
  158. CH3_INTCLEAR0
  159. CH3_INTCLEAR1
  160. CH3_INTCLEAR1
  161. CH3_INTSIGNAL_ENABLE0
  162. CH3_INTSIGNAL_ENABLE0
  163. CH3_INTSIGNAL_ENABLE1
  164. CH3_INTSIGNAL_ENABLE1
  165. CH3_INTSTATUS0
  166. CH3_INTSTATUS0
  167. CH3_INTSTATUS1
  168. CH3_INTSTATUS1
  169. CH3_INTSTATUS_ENABLE0
  170. CH3_INTSTATUS_ENABLE0
  171. CH3_INTSTATUS_ENABLE1
  172. CH3_INTSTATUS_ENABLE1
  173. CH3_LLP0
  174. CH3_LLP0
  175. CH3_LLP1
  176. CH3_LLP1
  177. CH3_SAR0
  178. CH3_SAR0
  179. CH3_SAR1
  180. CH3_SAR1
  181. CH3_SSTAT0
  182. CH3_SSTAT0
  183. CH3_SSTATAR0
  184. CH3_SSTATAR0
  185. CH3_SSTATAR1
  186. CH3_SSTATAR1
  187. CH3_STATUS0
  188. CH3_STATUS0
  189. CH3_STATUS1
  190. CH3_STATUS1
  191. CH3_SWHSDST0
  192. CH3_SWHSDST0
  193. CH3_SWHSSRC0
  194. CH3_SWHSSRC0
  195. CH4_AXI_ID0
  196. CH4_AXI_ID0
  197. CH4_AXI_QOS0
  198. CH4_AXI_QOS0
  199. CH4_BLK_TFR_RESUMEREQ0
  200. CH4_BLK_TFR_RESUMEREQ0
  201. CH4_BLOCK_TS0
  202. CH4_BLOCK_TS0
  203. CH4_CFG0
  204. CH4_CFG0
  205. CH4_CFG1
  206. CH4_CFG1
  207. CH4_CTL0
  208. CH4_CTL0
  209. CH4_CTL1
  210. CH4_CTL1
  211. CH4_DAR0
  212. CH4_DAR0
  213. CH4_DAR1
  214. CH4_DAR1
  215. CH4_DSTAT0
  216. CH4_DSTAT0
  217. CH4_DSTATAR0
  218. CH4_DSTATAR0
  219. CH4_DSTATAR1
  220. CH4_DSTATAR1
  221. CH4_INTCLEAR0
  222. CH4_INTCLEAR0
  223. CH4_INTCLEAR1
  224. CH4_INTCLEAR1
  225. CH4_INTSIGNAL_ENABLE0
  226. CH4_INTSIGNAL_ENABLE0
  227. CH4_INTSIGNAL_ENABLE1
  228. CH4_INTSIGNAL_ENABLE1
  229. CH4_INTSTATUS0
  230. CH4_INTSTATUS0
  231. CH4_INTSTATUS1
  232. CH4_INTSTATUS1
  233. CH4_INTSTATUS_ENABLE0
  234. CH4_INTSTATUS_ENABLE0
  235. CH4_INTSTATUS_ENABLE1
  236. CH4_INTSTATUS_ENABLE1
  237. CH4_LLP0
  238. CH4_LLP0
  239. CH4_LLP1
  240. CH4_LLP1
  241. CH4_SAR0
  242. CH4_SAR0
  243. CH4_SAR1
  244. CH4_SAR1
  245. CH4_SSTAT0
  246. CH4_SSTAT0
  247. CH4_SSTATAR0
  248. CH4_SSTATAR0
  249. CH4_SSTATAR1
  250. CH4_SSTATAR1
  251. CH4_STATUS0
  252. CH4_STATUS0
  253. CH4_STATUS1
  254. CH4_STATUS1
  255. CH4_SWHSDST0
  256. CH4_SWHSDST0
  257. CH4_SWHSSRC0
  258. CH4_SWHSSRC0
  259. CHEN0
  260. CHEN0
  261. CHEN1
  262. CHEN1
  263. COMMONREG_INTCLEAR0
  264. COMMONREG_INTCLEAR0
  265. COMMONREG_INTSIGNAL_ENABLE0
  266. COMMONREG_INTSIGNAL_ENABLE0
  267. COMMONREG_INTSTATUS0
  268. COMMONREG_INTSTATUS0
  269. COMMONREG_INTSTATUS_ENABLE0
  270. COMMONREG_INTSTATUS_ENABLE0
  271. COMPVER0
  272. COMPVER0
  273. ID0
  274. ID0
  275. INTSTATUS0
  276. INTSTATUS0
  277. LOWPOWER_CFG0
  278. LOWPOWER_CFG0
  279. LOWPOWER_CFG1
  280. LOWPOWER_CFG1
  281. RESET0
  282. RESET0