Regviz

Browse Registers In Our Database

Browse below to find the registers you are looking for, or search for one. For each register you can visualize its contents, and for many there is some basic reference information.

Registers in Espressif Systems /ESP32-P4 /H264_DMA

  1. COUNTER_RST
  2. COUNTER_RST
  3. DATE
  4. DATE
  5. EXTER_AXI_ERR
  6. EXTER_AXI_ERR
  7. EXTER_MEM_END_ADDR0
  8. EXTER_MEM_END_ADDR0
  9. EXTER_MEM_END_ADDR1
  10. EXTER_MEM_END_ADDR1
  11. EXTER_MEM_START_ADDR0
  12. EXTER_MEM_START_ADDR0
  13. EXTER_MEM_START_ADDR1
  14. EXTER_MEM_START_ADDR1
  15. IN_ARB_CH0
  16. IN_ARB_CH0
  17. IN_ARB_CH1
  18. IN_ARB_CH1
  19. IN_ARB_CH2
  20. IN_ARB_CH2
  21. IN_ARB_CH3
  22. IN_ARB_CH3
  23. IN_ARB_CH4
  24. IN_ARB_CH4
  25. IN_ARB_CH5
  26. IN_ARB_CH5
  27. IN_ARB_CONFIG
  28. IN_ARB_CONFIG
  29. IN_BUF_HB_RCV_CH0
  30. IN_BUF_HB_RCV_CH0
  31. IN_BUF_HB_RCV_CH1
  32. IN_BUF_HB_RCV_CH1
  33. IN_BUF_HB_RCV_CH2
  34. IN_BUF_HB_RCV_CH2
  35. IN_BUF_HB_RCV_CH3
  36. IN_BUF_HB_RCV_CH3
  37. IN_BUF_HB_RCV_CH4
  38. IN_BUF_HB_RCV_CH4
  39. IN_BUF_HB_RCV_CH5
  40. IN_BUF_HB_RCV_CH5
  41. IN_CONF0_CH0
  42. IN_CONF0_CH0
  43. IN_CONF0_CH1
  44. IN_CONF0_CH1
  45. IN_CONF0_CH2
  46. IN_CONF0_CH2
  47. IN_CONF0_CH3
  48. IN_CONF0_CH3
  49. IN_CONF0_CH4
  50. IN_CONF0_CH4
  51. IN_CONF0_CH5
  52. IN_CONF0_CH5
  53. IN_CONF1_CH5
  54. IN_CONF1_CH5
  55. IN_CONF2_CH5
  56. IN_CONF2_CH5
  57. IN_CONF3_CH5
  58. IN_CONF3_CH5
  59. IN_DSCR_BF0_CH0
  60. IN_DSCR_BF0_CH0
  61. IN_DSCR_BF0_CH1
  62. IN_DSCR_BF0_CH1
  63. IN_DSCR_BF0_CH2
  64. IN_DSCR_BF0_CH2
  65. IN_DSCR_BF0_CH3
  66. IN_DSCR_BF0_CH3
  67. IN_DSCR_BF0_CH4
  68. IN_DSCR_BF0_CH4
  69. IN_DSCR_BF1_CH0
  70. IN_DSCR_BF1_CH0
  71. IN_DSCR_BF1_CH1
  72. IN_DSCR_BF1_CH1
  73. IN_DSCR_BF1_CH2
  74. IN_DSCR_BF1_CH2
  75. IN_DSCR_BF1_CH3
  76. IN_DSCR_BF1_CH3
  77. IN_DSCR_BF1_CH4
  78. IN_DSCR_BF1_CH4
  79. IN_DSCR_CH0
  80. IN_DSCR_CH0
  81. IN_DSCR_CH1
  82. IN_DSCR_CH1
  83. IN_DSCR_CH2
  84. IN_DSCR_CH2
  85. IN_DSCR_CH3
  86. IN_DSCR_CH3
  87. IN_DSCR_CH4
  88. IN_DSCR_CH4
  89. IN_ERR_EOF_DES_ADDR_CH0
  90. IN_ERR_EOF_DES_ADDR_CH0
  91. IN_ERR_EOF_DES_ADDR_CH1
  92. IN_ERR_EOF_DES_ADDR_CH1
  93. IN_ERR_EOF_DES_ADDR_CH2
  94. IN_ERR_EOF_DES_ADDR_CH2
  95. IN_ERR_EOF_DES_ADDR_CH3
  96. IN_ERR_EOF_DES_ADDR_CH3
  97. IN_ERR_EOF_DES_ADDR_CH4
  98. IN_ERR_EOF_DES_ADDR_CH4
  99. IN_ETM_CONF_CH0
  100. IN_ETM_CONF_CH0
  101. IN_ETM_CONF_CH1
  102. IN_ETM_CONF_CH1
  103. IN_ETM_CONF_CH2
  104. IN_ETM_CONF_CH2
  105. IN_ETM_CONF_CH3
  106. IN_ETM_CONF_CH3
  107. IN_ETM_CONF_CH4
  108. IN_ETM_CONF_CH4
  109. IN_FIFO_CNT_CH0
  110. IN_FIFO_CNT_CH0
  111. IN_FIFO_CNT_CH1
  112. IN_FIFO_CNT_CH1
  113. IN_FIFO_CNT_CH2
  114. IN_FIFO_CNT_CH2
  115. IN_FIFO_CNT_CH3
  116. IN_FIFO_CNT_CH3
  117. IN_FIFO_CNT_CH4
  118. IN_FIFO_CNT_CH4
  119. IN_FIFO_CNT_CH5
  120. IN_FIFO_CNT_CH5
  121. INFIFO_STATUS_CH0
  122. INFIFO_STATUS_CH0
  123. INFIFO_STATUS_CH1
  124. INFIFO_STATUS_CH1
  125. INFIFO_STATUS_CH2
  126. INFIFO_STATUS_CH2
  127. INFIFO_STATUS_CH3
  128. INFIFO_STATUS_CH3
  129. INFIFO_STATUS_CH4
  130. INFIFO_STATUS_CH4
  131. INFIFO_STATUS_CH5
  132. INFIFO_STATUS_CH5
  133. IN_INT_CLR_CH0
  134. IN_INT_CLR_CH0
  135. IN_INT_CLR_CH1
  136. IN_INT_CLR_CH1
  137. IN_INT_CLR_CH2
  138. IN_INT_CLR_CH2
  139. IN_INT_CLR_CH3
  140. IN_INT_CLR_CH3
  141. IN_INT_CLR_CH4
  142. IN_INT_CLR_CH4
  143. IN_INT_CLR_CH5
  144. IN_INT_CLR_CH5
  145. IN_INT_ENA_CH0
  146. IN_INT_ENA_CH0
  147. IN_INT_ENA_CH1
  148. IN_INT_ENA_CH1
  149. IN_INT_ENA_CH2
  150. IN_INT_ENA_CH2
  151. IN_INT_ENA_CH3
  152. IN_INT_ENA_CH3
  153. IN_INT_ENA_CH4
  154. IN_INT_ENA_CH4
  155. IN_INT_ENA_CH5
  156. IN_INT_ENA_CH5
  157. IN_INT_RAW_CH0
  158. IN_INT_RAW_CH0
  159. IN_INT_RAW_CH1
  160. IN_INT_RAW_CH1
  161. IN_INT_RAW_CH2
  162. IN_INT_RAW_CH2
  163. IN_INT_RAW_CH3
  164. IN_INT_RAW_CH3
  165. IN_INT_RAW_CH4
  166. IN_INT_RAW_CH4
  167. IN_INT_RAW_CH5
  168. IN_INT_RAW_CH5
  169. IN_INT_ST_CH0
  170. IN_INT_ST_CH0
  171. IN_INT_ST_CH1
  172. IN_INT_ST_CH1
  173. IN_INT_ST_CH2
  174. IN_INT_ST_CH2
  175. IN_INT_ST_CH3
  176. IN_INT_ST_CH3
  177. IN_INT_ST_CH4
  178. IN_INT_ST_CH4
  179. IN_INT_ST_CH5
  180. IN_INT_ST_CH5
  181. IN_LINK_ADDR_CH0
  182. IN_LINK_ADDR_CH0
  183. IN_LINK_ADDR_CH1
  184. IN_LINK_ADDR_CH1
  185. IN_LINK_ADDR_CH2
  186. IN_LINK_ADDR_CH2
  187. IN_LINK_ADDR_CH3
  188. IN_LINK_ADDR_CH3
  189. IN_LINK_ADDR_CH4
  190. IN_LINK_ADDR_CH4
  191. IN_LINK_CONF_CH0
  192. IN_LINK_CONF_CH0
  193. IN_LINK_CONF_CH1
  194. IN_LINK_CONF_CH1
  195. IN_LINK_CONF_CH2
  196. IN_LINK_CONF_CH2
  197. IN_LINK_CONF_CH3
  198. IN_LINK_CONF_CH3
  199. IN_LINK_CONF_CH4
  200. IN_LINK_CONF_CH4
  201. IN_POP_CH0
  202. IN_POP_CH0
  203. IN_POP_CH1
  204. IN_POP_CH1
  205. IN_POP_CH2
  206. IN_POP_CH2
  207. IN_POP_CH3
  208. IN_POP_CH3
  209. IN_POP_CH4
  210. IN_POP_CH4
  211. IN_POP_CH5
  212. IN_POP_CH5
  213. IN_POP_DATA_CNT_CH0
  214. IN_POP_DATA_CNT_CH0
  215. IN_POP_DATA_CNT_CH1
  216. IN_POP_DATA_CNT_CH1
  217. IN_POP_DATA_CNT_CH2
  218. IN_POP_DATA_CNT_CH2
  219. IN_POP_DATA_CNT_CH3
  220. IN_POP_DATA_CNT_CH3
  221. IN_POP_DATA_CNT_CH4
  222. IN_POP_DATA_CNT_CH4
  223. IN_POP_DATA_CNT_CH5
  224. IN_POP_DATA_CNT_CH5
  225. IN_RO_PD_CONF_CH0
  226. IN_RO_PD_CONF_CH0
  227. IN_STATE_CH0
  228. IN_STATE_CH0
  229. IN_STATE_CH1
  230. IN_STATE_CH1
  231. IN_STATE_CH2
  232. IN_STATE_CH2
  233. IN_STATE_CH3
  234. IN_STATE_CH3
  235. IN_STATE_CH4
  236. IN_STATE_CH4
  237. IN_STATE_CH5
  238. IN_STATE_CH5
  239. IN_SUC_EOF_DES_ADDR_CH0
  240. IN_SUC_EOF_DES_ADDR_CH0
  241. IN_SUC_EOF_DES_ADDR_CH1
  242. IN_SUC_EOF_DES_ADDR_CH1
  243. IN_SUC_EOF_DES_ADDR_CH2
  244. IN_SUC_EOF_DES_ADDR_CH2
  245. IN_SUC_EOF_DES_ADDR_CH3
  246. IN_SUC_EOF_DES_ADDR_CH3
  247. IN_SUC_EOF_DES_ADDR_CH4
  248. IN_SUC_EOF_DES_ADDR_CH4
  249. INTER_AXI_ERR
  250. INTER_AXI_ERR
  251. INTER_MEM_END_ADDR0
  252. INTER_MEM_END_ADDR0
  253. INTER_MEM_END_ADDR1
  254. INTER_MEM_END_ADDR1
  255. INTER_MEM_START_ADDR0
  256. INTER_MEM_START_ADDR0
  257. INTER_MEM_START_ADDR1
  258. INTER_MEM_START_ADDR1
  259. IN_XADDR_CH0
  260. IN_XADDR_CH0
  261. IN_XADDR_CH1
  262. IN_XADDR_CH1
  263. IN_XADDR_CH2
  264. IN_XADDR_CH2
  265. IN_XADDR_CH3
  266. IN_XADDR_CH3
  267. IN_XADDR_CH4
  268. IN_XADDR_CH4
  269. IN_XADDR_CH5
  270. IN_XADDR_CH5
  271. OUT_ARB_CH0
  272. OUT_ARB_CH0
  273. OUT_ARB_CH1
  274. OUT_ARB_CH1
  275. OUT_ARB_CH2
  276. OUT_ARB_CH2
  277. OUT_ARB_CH3
  278. OUT_ARB_CH3
  279. OUT_ARB_CH4
  280. OUT_ARB_CH4
  281. OUT_ARB_CONFIG
  282. OUT_ARB_CONFIG
  283. OUT_BLOCK_BUF_LEN_CH3
  284. OUT_BLOCK_BUF_LEN_CH3
  285. OUT_BLOCK_BUF_LEN_CH4
  286. OUT_BLOCK_BUF_LEN_CH4
  287. OUT_BUF_LEN_CH0
  288. OUT_BUF_LEN_CH0
  289. OUT_BUF_LEN_CH1
  290. OUT_BUF_LEN_CH1
  291. OUT_BUF_LEN_CH2
  292. OUT_BUF_LEN_CH2
  293. OUT_BUF_LEN_CH3
  294. OUT_BUF_LEN_CH3
  295. OUT_BUF_LEN_CH4
  296. OUT_BUF_LEN_CH4
  297. OUT_CONF0_CH0
  298. OUT_CONF0_CH0
  299. OUT_CONF0_CH1
  300. OUT_CONF0_CH1
  301. OUT_CONF0_CH2
  302. OUT_CONF0_CH2
  303. OUT_CONF0_CH3
  304. OUT_CONF0_CH3
  305. OUT_CONF0_CH4
  306. OUT_CONF0_CH4
  307. OUT_DSCR_BF0_CH0
  308. OUT_DSCR_BF0_CH0
  309. OUT_DSCR_BF0_CH1
  310. OUT_DSCR_BF0_CH1
  311. OUT_DSCR_BF0_CH2
  312. OUT_DSCR_BF0_CH2
  313. OUT_DSCR_BF0_CH3
  314. OUT_DSCR_BF0_CH3
  315. OUT_DSCR_BF0_CH4
  316. OUT_DSCR_BF0_CH4
  317. OUT_DSCR_BF1_CH0
  318. OUT_DSCR_BF1_CH0
  319. OUT_DSCR_BF1_CH1
  320. OUT_DSCR_BF1_CH1
  321. OUT_DSCR_BF1_CH2
  322. OUT_DSCR_BF1_CH2
  323. OUT_DSCR_BF1_CH3
  324. OUT_DSCR_BF1_CH3
  325. OUT_DSCR_BF1_CH4
  326. OUT_DSCR_BF1_CH4
  327. OUT_DSCR_CH0
  328. OUT_DSCR_CH0
  329. OUT_DSCR_CH1
  330. OUT_DSCR_CH1
  331. OUT_DSCR_CH2
  332. OUT_DSCR_CH2
  333. OUT_DSCR_CH3
  334. OUT_DSCR_CH3
  335. OUT_DSCR_CH4
  336. OUT_DSCR_CH4
  337. OUT_EOF_DES_ADDR_CH0
  338. OUT_EOF_DES_ADDR_CH0
  339. OUT_EOF_DES_ADDR_CH1
  340. OUT_EOF_DES_ADDR_CH1
  341. OUT_EOF_DES_ADDR_CH2
  342. OUT_EOF_DES_ADDR_CH2
  343. OUT_EOF_DES_ADDR_CH3
  344. OUT_EOF_DES_ADDR_CH3
  345. OUT_EOF_DES_ADDR_CH4
  346. OUT_EOF_DES_ADDR_CH4
  347. OUT_ETM_CONF_CH0
  348. OUT_ETM_CONF_CH0
  349. OUT_ETM_CONF_CH1
  350. OUT_ETM_CONF_CH1
  351. OUT_ETM_CONF_CH2
  352. OUT_ETM_CONF_CH2
  353. OUT_ETM_CONF_CH3
  354. OUT_ETM_CONF_CH3
  355. OUT_ETM_CONF_CH4
  356. OUT_ETM_CONF_CH4
  357. OUT_FIFO_BCNT_CH0
  358. OUT_FIFO_BCNT_CH0
  359. OUT_FIFO_BCNT_CH1
  360. OUT_FIFO_BCNT_CH1
  361. OUT_FIFO_BCNT_CH2
  362. OUT_FIFO_BCNT_CH2
  363. OUT_FIFO_BCNT_CH3
  364. OUT_FIFO_BCNT_CH3
  365. OUT_FIFO_BCNT_CH4
  366. OUT_FIFO_BCNT_CH4
  367. OUTFIFO_STATUS_CH0
  368. OUTFIFO_STATUS_CH0
  369. OUTFIFO_STATUS_CH1
  370. OUTFIFO_STATUS_CH1
  371. OUTFIFO_STATUS_CH2
  372. OUTFIFO_STATUS_CH2
  373. OUTFIFO_STATUS_CH3
  374. OUTFIFO_STATUS_CH3
  375. OUTFIFO_STATUS_CH4
  376. OUTFIFO_STATUS_CH4
  377. OUT_INT_CLR_CH0
  378. OUT_INT_CLR_CH0
  379. OUT_INT_CLR_CH1
  380. OUT_INT_CLR_CH1
  381. OUT_INT_CLR_CH2
  382. OUT_INT_CLR_CH2
  383. OUT_INT_CLR_CH3
  384. OUT_INT_CLR_CH3
  385. OUT_INT_CLR_CH4
  386. OUT_INT_CLR_CH4
  387. OUT_INT_ENA_CH0
  388. OUT_INT_ENA_CH0
  389. OUT_INT_ENA_CH1
  390. OUT_INT_ENA_CH1
  391. OUT_INT_ENA_CH2
  392. OUT_INT_ENA_CH2
  393. OUT_INT_ENA_CH3
  394. OUT_INT_ENA_CH3
  395. OUT_INT_ENA_CH4
  396. OUT_INT_ENA_CH4
  397. OUT_INT_RAW_CH0
  398. OUT_INT_RAW_CH0
  399. OUT_INT_RAW_CH1
  400. OUT_INT_RAW_CH1
  401. OUT_INT_RAW_CH2
  402. OUT_INT_RAW_CH2
  403. OUT_INT_RAW_CH3
  404. OUT_INT_RAW_CH3
  405. OUT_INT_RAW_CH4
  406. OUT_INT_RAW_CH4
  407. OUT_INT_ST_CH0
  408. OUT_INT_ST_CH0
  409. OUT_INT_ST_CH1
  410. OUT_INT_ST_CH1
  411. OUT_INT_ST_CH2
  412. OUT_INT_ST_CH2
  413. OUT_INT_ST_CH3
  414. OUT_INT_ST_CH3
  415. OUT_INT_ST_CH4
  416. OUT_INT_ST_CH4
  417. OUT_LINK_ADDR_CH0
  418. OUT_LINK_ADDR_CH0
  419. OUT_LINK_ADDR_CH1
  420. OUT_LINK_ADDR_CH1
  421. OUT_LINK_ADDR_CH2
  422. OUT_LINK_ADDR_CH2
  423. OUT_LINK_ADDR_CH3
  424. OUT_LINK_ADDR_CH3
  425. OUT_LINK_ADDR_CH4
  426. OUT_LINK_ADDR_CH4
  427. OUT_LINK_CONF_CH0
  428. OUT_LINK_CONF_CH0
  429. OUT_LINK_CONF_CH1
  430. OUT_LINK_CONF_CH1
  431. OUT_LINK_CONF_CH2
  432. OUT_LINK_CONF_CH2
  433. OUT_LINK_CONF_CH3
  434. OUT_LINK_CONF_CH3
  435. OUT_LINK_CONF_CH4
  436. OUT_LINK_CONF_CH4
  437. OUT_MODE_ENABLE_CH0
  438. OUT_MODE_ENABLE_CH0
  439. OUT_MODE_YUV_CH0
  440. OUT_MODE_YUV_CH0
  441. OUT_PUSH_BYTECNT_CH0
  442. OUT_PUSH_BYTECNT_CH0
  443. OUT_PUSH_BYTECNT_CH1
  444. OUT_PUSH_BYTECNT_CH1
  445. OUT_PUSH_BYTECNT_CH2
  446. OUT_PUSH_BYTECNT_CH2
  447. OUT_PUSH_BYTECNT_CH3
  448. OUT_PUSH_BYTECNT_CH3
  449. OUT_PUSH_BYTECNT_CH4
  450. OUT_PUSH_BYTECNT_CH4
  451. OUT_PUSH_CH0
  452. OUT_PUSH_CH0
  453. OUT_PUSH_CH1
  454. OUT_PUSH_CH1
  455. OUT_PUSH_CH2
  456. OUT_PUSH_CH2
  457. OUT_PUSH_CH3
  458. OUT_PUSH_CH3
  459. OUT_PUSH_CH4
  460. OUT_PUSH_CH4
  461. OUT_RO_PD_CONF_CH0
  462. OUT_RO_PD_CONF_CH0
  463. OUT_RO_STATUS_CH0
  464. OUT_RO_STATUS_CH0
  465. OUT_STATE_CH0
  466. OUT_STATE_CH0
  467. OUT_STATE_CH1
  468. OUT_STATE_CH1
  469. OUT_STATE_CH2
  470. OUT_STATE_CH2
  471. OUT_STATE_CH3
  472. OUT_STATE_CH3
  473. OUT_STATE_CH4
  474. OUT_STATE_CH4
  475. OUT_XADDR_CH0
  476. OUT_XADDR_CH0
  477. OUT_XADDR_CH1
  478. OUT_XADDR_CH1
  479. OUT_XADDR_CH2
  480. OUT_XADDR_CH2
  481. OUT_XADDR_CH3
  482. OUT_XADDR_CH3
  483. OUT_XADDR_CH4
  484. OUT_XADDR_CH4
  485. RST_CONF
  486. RST_CONF
  487. RX_CH0_COUNTER
  488. RX_CH0_COUNTER
  489. RX_CH1_COUNTER
  490. RX_CH1_COUNTER
  491. RX_CH2_COUNTER
  492. RX_CH2_COUNTER
  493. RX_CH5_COUNTER
  494. RX_CH5_COUNTER