Regviz

Browse Registers In Our Database

Browse below to find the registers you are looking for, or search for one. For each register you can visualize its contents, and for many there is some basic reference information.

Registers in Espressif Systems /ESP32-S3 /SENSITIVE

  1. APB_PERIPHERAL_ACCESS_0
  2. APB_PERIPHERAL_ACCESS_0
  3. APB_PERIPHERAL_ACCESS_1
  4. APB_PERIPHERAL_ACCESS_1
  5. BACKUP_BUS_PMS_CONSTRAIN_0
  6. BACKUP_BUS_PMS_CONSTRAIN_0
  7. BACKUP_BUS_PMS_CONSTRAIN_1
  8. BACKUP_BUS_PMS_CONSTRAIN_1
  9. BACKUP_BUS_PMS_CONSTRAIN_2
  10. BACKUP_BUS_PMS_CONSTRAIN_2
  11. BACKUP_BUS_PMS_CONSTRAIN_3
  12. BACKUP_BUS_PMS_CONSTRAIN_3
  13. BACKUP_BUS_PMS_CONSTRAIN_4
  14. BACKUP_BUS_PMS_CONSTRAIN_4
  15. BACKUP_BUS_PMS_CONSTRAIN_5
  16. BACKUP_BUS_PMS_CONSTRAIN_5
  17. BACKUP_BUS_PMS_CONSTRAIN_6
  18. BACKUP_BUS_PMS_CONSTRAIN_6
  19. BACKUP_BUS_PMS_MONITOR_0
  20. BACKUP_BUS_PMS_MONITOR_0
  21. BACKUP_BUS_PMS_MONITOR_1
  22. BACKUP_BUS_PMS_MONITOR_1
  23. BACKUP_BUS_PMS_MONITOR_2
  24. BACKUP_BUS_PMS_MONITOR_2
  25. BACKUP_BUS_PMS_MONITOR_3
  26. BACKUP_BUS_PMS_MONITOR_3
  27. CACHE_DATAARRAY_CONNECT_0
  28. CACHE_DATAARRAY_CONNECT_0
  29. CACHE_DATAARRAY_CONNECT_1
  30. CACHE_DATAARRAY_CONNECT_1
  31. CACHE_MMU_ACCESS_0
  32. CACHE_MMU_ACCESS_0
  33. CACHE_MMU_ACCESS_1
  34. CACHE_MMU_ACCESS_1
  35. CACHE_TAG_ACCESS_0
  36. CACHE_TAG_ACCESS_0
  37. CACHE_TAG_ACCESS_1
  38. CACHE_TAG_ACCESS_1
  39. CLOCK_GATE
  40. CLOCK_GATE
  41. CORE_0_DRAM0_PMS_MONITOR_0
  42. CORE_0_DRAM0_PMS_MONITOR_0
  43. CORE_0_DRAM0_PMS_MONITOR_1
  44. CORE_0_DRAM0_PMS_MONITOR_1
  45. CORE_0_DRAM0_PMS_MONITOR_2
  46. CORE_0_DRAM0_PMS_MONITOR_2
  47. CORE_0_DRAM0_PMS_MONITOR_3
  48. CORE_0_DRAM0_PMS_MONITOR_3
  49. CORE_0_IRAM0_PMS_MONITOR_0
  50. CORE_0_IRAM0_PMS_MONITOR_0
  51. CORE_0_IRAM0_PMS_MONITOR_1
  52. CORE_0_IRAM0_PMS_MONITOR_1
  53. CORE_0_IRAM0_PMS_MONITOR_2
  54. CORE_0_IRAM0_PMS_MONITOR_2
  55. CORE_0_PIF_PMS_CONSTRAIN_0
  56. CORE_0_PIF_PMS_CONSTRAIN_0
  57. CORE_0_PIF_PMS_CONSTRAIN_1
  58. CORE_0_PIF_PMS_CONSTRAIN_1
  59. CORE_0_PIF_PMS_CONSTRAIN_10
  60. CORE_0_PIF_PMS_CONSTRAIN_10
  61. CORE_0_PIF_PMS_CONSTRAIN_11
  62. CORE_0_PIF_PMS_CONSTRAIN_11
  63. CORE_0_PIF_PMS_CONSTRAIN_12
  64. CORE_0_PIF_PMS_CONSTRAIN_12
  65. CORE_0_PIF_PMS_CONSTRAIN_13
  66. CORE_0_PIF_PMS_CONSTRAIN_13
  67. CORE_0_PIF_PMS_CONSTRAIN_14
  68. CORE_0_PIF_PMS_CONSTRAIN_14
  69. CORE_0_PIF_PMS_CONSTRAIN_2
  70. CORE_0_PIF_PMS_CONSTRAIN_2
  71. CORE_0_PIF_PMS_CONSTRAIN_3
  72. CORE_0_PIF_PMS_CONSTRAIN_3
  73. CORE_0_PIF_PMS_CONSTRAIN_4
  74. CORE_0_PIF_PMS_CONSTRAIN_4
  75. CORE_0_PIF_PMS_CONSTRAIN_5
  76. CORE_0_PIF_PMS_CONSTRAIN_5
  77. CORE_0_PIF_PMS_CONSTRAIN_6
  78. CORE_0_PIF_PMS_CONSTRAIN_6
  79. CORE_0_PIF_PMS_CONSTRAIN_7
  80. CORE_0_PIF_PMS_CONSTRAIN_7
  81. CORE_0_PIF_PMS_CONSTRAIN_8
  82. CORE_0_PIF_PMS_CONSTRAIN_8
  83. CORE_0_PIF_PMS_CONSTRAIN_9
  84. CORE_0_PIF_PMS_CONSTRAIN_9
  85. CORE_0_PIF_PMS_MONITOR_0
  86. CORE_0_PIF_PMS_MONITOR_0
  87. CORE_0_PIF_PMS_MONITOR_1
  88. CORE_0_PIF_PMS_MONITOR_1
  89. CORE_0_PIF_PMS_MONITOR_2
  90. CORE_0_PIF_PMS_MONITOR_2
  91. CORE_0_PIF_PMS_MONITOR_3
  92. CORE_0_PIF_PMS_MONITOR_3
  93. CORE_0_PIF_PMS_MONITOR_4
  94. CORE_0_PIF_PMS_MONITOR_4
  95. CORE_0_PIF_PMS_MONITOR_5
  96. CORE_0_PIF_PMS_MONITOR_5
  97. CORE_0_PIF_PMS_MONITOR_6
  98. CORE_0_PIF_PMS_MONITOR_6
  99. CORE_0_REGION_PMS_CONSTRAIN_0
  100. CORE_0_REGION_PMS_CONSTRAIN_0
  101. CORE_0_REGION_PMS_CONSTRAIN_1
  102. CORE_0_REGION_PMS_CONSTRAIN_1
  103. CORE_0_REGION_PMS_CONSTRAIN_10
  104. CORE_0_REGION_PMS_CONSTRAIN_10
  105. CORE_0_REGION_PMS_CONSTRAIN_11
  106. CORE_0_REGION_PMS_CONSTRAIN_11
  107. CORE_0_REGION_PMS_CONSTRAIN_12
  108. CORE_0_REGION_PMS_CONSTRAIN_12
  109. CORE_0_REGION_PMS_CONSTRAIN_13
  110. CORE_0_REGION_PMS_CONSTRAIN_13
  111. CORE_0_REGION_PMS_CONSTRAIN_14
  112. CORE_0_REGION_PMS_CONSTRAIN_14
  113. CORE_0_REGION_PMS_CONSTRAIN_2
  114. CORE_0_REGION_PMS_CONSTRAIN_2
  115. CORE_0_REGION_PMS_CONSTRAIN_3
  116. CORE_0_REGION_PMS_CONSTRAIN_3
  117. CORE_0_REGION_PMS_CONSTRAIN_4
  118. CORE_0_REGION_PMS_CONSTRAIN_4
  119. CORE_0_REGION_PMS_CONSTRAIN_5
  120. CORE_0_REGION_PMS_CONSTRAIN_5
  121. CORE_0_REGION_PMS_CONSTRAIN_6
  122. CORE_0_REGION_PMS_CONSTRAIN_6
  123. CORE_0_REGION_PMS_CONSTRAIN_7
  124. CORE_0_REGION_PMS_CONSTRAIN_7
  125. CORE_0_REGION_PMS_CONSTRAIN_8
  126. CORE_0_REGION_PMS_CONSTRAIN_8
  127. CORE_0_REGION_PMS_CONSTRAIN_9
  128. CORE_0_REGION_PMS_CONSTRAIN_9
  129. CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0
  130. CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0
  131. CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1
  132. CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1
  133. CORE_0_VECBASE_OVERRIDE_0
  134. CORE_0_VECBASE_OVERRIDE_0
  135. CORE_0_VECBASE_OVERRIDE_1
  136. CORE_0_VECBASE_OVERRIDE_1
  137. CORE_0_VECBASE_OVERRIDE_2
  138. CORE_0_VECBASE_OVERRIDE_2
  139. CORE_0_VECBASE_OVERRIDE_LOCK
  140. CORE_0_VECBASE_OVERRIDE_LOCK
  141. CORE_1_DRAM0_PMS_MONITOR_0
  142. CORE_1_DRAM0_PMS_MONITOR_0
  143. CORE_1_DRAM0_PMS_MONITOR_1
  144. CORE_1_DRAM0_PMS_MONITOR_1
  145. CORE_1_DRAM0_PMS_MONITOR_2
  146. CORE_1_DRAM0_PMS_MONITOR_2
  147. CORE_1_DRAM0_PMS_MONITOR_3
  148. CORE_1_DRAM0_PMS_MONITOR_3
  149. CORE_1_IRAM0_PMS_MONITOR_0
  150. CORE_1_IRAM0_PMS_MONITOR_0
  151. CORE_1_IRAM0_PMS_MONITOR_1
  152. CORE_1_IRAM0_PMS_MONITOR_1
  153. CORE_1_IRAM0_PMS_MONITOR_2
  154. CORE_1_IRAM0_PMS_MONITOR_2
  155. CORE_1_PIF_PMS_CONSTRAIN_0
  156. CORE_1_PIF_PMS_CONSTRAIN_0
  157. CORE_1_PIF_PMS_CONSTRAIN_1
  158. CORE_1_PIF_PMS_CONSTRAIN_1
  159. CORE_1_PIF_PMS_CONSTRAIN_10
  160. CORE_1_PIF_PMS_CONSTRAIN_10
  161. CORE_1_PIF_PMS_CONSTRAIN_11
  162. CORE_1_PIF_PMS_CONSTRAIN_11
  163. CORE_1_PIF_PMS_CONSTRAIN_12
  164. CORE_1_PIF_PMS_CONSTRAIN_12
  165. CORE_1_PIF_PMS_CONSTRAIN_13
  166. CORE_1_PIF_PMS_CONSTRAIN_13
  167. CORE_1_PIF_PMS_CONSTRAIN_14
  168. CORE_1_PIF_PMS_CONSTRAIN_14
  169. CORE_1_PIF_PMS_CONSTRAIN_2
  170. CORE_1_PIF_PMS_CONSTRAIN_2
  171. CORE_1_PIF_PMS_CONSTRAIN_3
  172. CORE_1_PIF_PMS_CONSTRAIN_3
  173. CORE_1_PIF_PMS_CONSTRAIN_4
  174. CORE_1_PIF_PMS_CONSTRAIN_4
  175. CORE_1_PIF_PMS_CONSTRAIN_5
  176. CORE_1_PIF_PMS_CONSTRAIN_5
  177. CORE_1_PIF_PMS_CONSTRAIN_6
  178. CORE_1_PIF_PMS_CONSTRAIN_6
  179. CORE_1_PIF_PMS_CONSTRAIN_7
  180. CORE_1_PIF_PMS_CONSTRAIN_7
  181. CORE_1_PIF_PMS_CONSTRAIN_8
  182. CORE_1_PIF_PMS_CONSTRAIN_8
  183. CORE_1_PIF_PMS_CONSTRAIN_9
  184. CORE_1_PIF_PMS_CONSTRAIN_9
  185. CORE_1_PIF_PMS_MONITOR_0
  186. CORE_1_PIF_PMS_MONITOR_0
  187. CORE_1_PIF_PMS_MONITOR_1
  188. CORE_1_PIF_PMS_MONITOR_1
  189. CORE_1_PIF_PMS_MONITOR_2
  190. CORE_1_PIF_PMS_MONITOR_2
  191. CORE_1_PIF_PMS_MONITOR_3
  192. CORE_1_PIF_PMS_MONITOR_3
  193. CORE_1_PIF_PMS_MONITOR_4
  194. CORE_1_PIF_PMS_MONITOR_4
  195. CORE_1_PIF_PMS_MONITOR_5
  196. CORE_1_PIF_PMS_MONITOR_5
  197. CORE_1_PIF_PMS_MONITOR_6
  198. CORE_1_PIF_PMS_MONITOR_6
  199. CORE_1_REGION_PMS_CONSTRAIN_0
  200. CORE_1_REGION_PMS_CONSTRAIN_0
  201. CORE_1_REGION_PMS_CONSTRAIN_1
  202. CORE_1_REGION_PMS_CONSTRAIN_1
  203. CORE_1_REGION_PMS_CONSTRAIN_10
  204. CORE_1_REGION_PMS_CONSTRAIN_10
  205. CORE_1_REGION_PMS_CONSTRAIN_11
  206. CORE_1_REGION_PMS_CONSTRAIN_11
  207. CORE_1_REGION_PMS_CONSTRAIN_12
  208. CORE_1_REGION_PMS_CONSTRAIN_12
  209. CORE_1_REGION_PMS_CONSTRAIN_13
  210. CORE_1_REGION_PMS_CONSTRAIN_13
  211. CORE_1_REGION_PMS_CONSTRAIN_14
  212. CORE_1_REGION_PMS_CONSTRAIN_14
  213. CORE_1_REGION_PMS_CONSTRAIN_2
  214. CORE_1_REGION_PMS_CONSTRAIN_2
  215. CORE_1_REGION_PMS_CONSTRAIN_3
  216. CORE_1_REGION_PMS_CONSTRAIN_3
  217. CORE_1_REGION_PMS_CONSTRAIN_4
  218. CORE_1_REGION_PMS_CONSTRAIN_4
  219. CORE_1_REGION_PMS_CONSTRAIN_5
  220. CORE_1_REGION_PMS_CONSTRAIN_5
  221. CORE_1_REGION_PMS_CONSTRAIN_6
  222. CORE_1_REGION_PMS_CONSTRAIN_6
  223. CORE_1_REGION_PMS_CONSTRAIN_7
  224. CORE_1_REGION_PMS_CONSTRAIN_7
  225. CORE_1_REGION_PMS_CONSTRAIN_8
  226. CORE_1_REGION_PMS_CONSTRAIN_8
  227. CORE_1_REGION_PMS_CONSTRAIN_9
  228. CORE_1_REGION_PMS_CONSTRAIN_9
  229. CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0
  230. CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0
  231. CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1
  232. CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1
  233. CORE_1_VECBASE_OVERRIDE_0
  234. CORE_1_VECBASE_OVERRIDE_0
  235. CORE_1_VECBASE_OVERRIDE_1
  236. CORE_1_VECBASE_OVERRIDE_1
  237. CORE_1_VECBASE_OVERRIDE_2
  238. CORE_1_VECBASE_OVERRIDE_2
  239. CORE_1_VECBASE_OVERRIDE_LOCK
  240. CORE_1_VECBASE_OVERRIDE_LOCK
  241. CORE_X_DRAM0_PMS_CONSTRAIN_0
  242. CORE_X_DRAM0_PMS_CONSTRAIN_0
  243. CORE_X_DRAM0_PMS_CONSTRAIN_1
  244. CORE_X_DRAM0_PMS_CONSTRAIN_1
  245. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0
  246. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0
  247. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1
  248. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1
  249. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2
  250. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2
  251. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3
  252. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3
  253. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4
  254. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4
  255. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5
  256. CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5
  257. CORE_X_IRAM0_PMS_CONSTRAIN_0
  258. CORE_X_IRAM0_PMS_CONSTRAIN_0
  259. CORE_X_IRAM0_PMS_CONSTRAIN_1
  260. CORE_X_IRAM0_PMS_CONSTRAIN_1
  261. CORE_X_IRAM0_PMS_CONSTRAIN_2
  262. CORE_X_IRAM0_PMS_CONSTRAIN_2
  263. DATE
  264. DATE
  265. DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0
  266. DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0
  267. DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1
  268. DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1
  269. DMA_APBPERI_AES_PMS_CONSTRAIN_0
  270. DMA_APBPERI_AES_PMS_CONSTRAIN_0
  271. DMA_APBPERI_AES_PMS_CONSTRAIN_1
  272. DMA_APBPERI_AES_PMS_CONSTRAIN_1
  273. DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0
  274. DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0
  275. DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1
  276. DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1
  277. DMA_APBPERI_I2S0_PMS_CONSTRAIN_0
  278. DMA_APBPERI_I2S0_PMS_CONSTRAIN_0
  279. DMA_APBPERI_I2S0_PMS_CONSTRAIN_1
  280. DMA_APBPERI_I2S0_PMS_CONSTRAIN_1
  281. DMA_APBPERI_I2S1_PMS_CONSTRAIN_0
  282. DMA_APBPERI_I2S1_PMS_CONSTRAIN_0
  283. DMA_APBPERI_I2S1_PMS_CONSTRAIN_1
  284. DMA_APBPERI_I2S1_PMS_CONSTRAIN_1
  285. DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0
  286. DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0
  287. DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1
  288. DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1
  289. DMA_APBPERI_LC_PMS_CONSTRAIN_0
  290. DMA_APBPERI_LC_PMS_CONSTRAIN_0
  291. DMA_APBPERI_LC_PMS_CONSTRAIN_1
  292. DMA_APBPERI_LC_PMS_CONSTRAIN_1
  293. DMA_APBPERI_MAC_PMS_CONSTRAIN_0
  294. DMA_APBPERI_MAC_PMS_CONSTRAIN_0
  295. DMA_APBPERI_MAC_PMS_CONSTRAIN_1
  296. DMA_APBPERI_MAC_PMS_CONSTRAIN_1
  297. DMA_APBPERI_PMS_MONITOR_0
  298. DMA_APBPERI_PMS_MONITOR_0
  299. DMA_APBPERI_PMS_MONITOR_1
  300. DMA_APBPERI_PMS_MONITOR_1
  301. DMA_APBPERI_PMS_MONITOR_2
  302. DMA_APBPERI_PMS_MONITOR_2
  303. DMA_APBPERI_PMS_MONITOR_3
  304. DMA_APBPERI_PMS_MONITOR_3
  305. DMA_APBPERI_RMT_PMS_CONSTRAIN_0
  306. DMA_APBPERI_RMT_PMS_CONSTRAIN_0
  307. DMA_APBPERI_RMT_PMS_CONSTRAIN_1
  308. DMA_APBPERI_RMT_PMS_CONSTRAIN_1
  309. DMA_APBPERI_SDIO_PMS_CONSTRAIN_0
  310. DMA_APBPERI_SDIO_PMS_CONSTRAIN_0
  311. DMA_APBPERI_SDIO_PMS_CONSTRAIN_1
  312. DMA_APBPERI_SDIO_PMS_CONSTRAIN_1
  313. DMA_APBPERI_SHA_PMS_CONSTRAIN_0
  314. DMA_APBPERI_SHA_PMS_CONSTRAIN_0
  315. DMA_APBPERI_SHA_PMS_CONSTRAIN_1
  316. DMA_APBPERI_SHA_PMS_CONSTRAIN_1
  317. DMA_APBPERI_SPI2_PMS_CONSTRAIN_0
  318. DMA_APBPERI_SPI2_PMS_CONSTRAIN_0
  319. DMA_APBPERI_SPI2_PMS_CONSTRAIN_1
  320. DMA_APBPERI_SPI2_PMS_CONSTRAIN_1
  321. DMA_APBPERI_SPI3_PMS_CONSTRAIN_0
  322. DMA_APBPERI_SPI3_PMS_CONSTRAIN_0
  323. DMA_APBPERI_SPI3_PMS_CONSTRAIN_1
  324. DMA_APBPERI_SPI3_PMS_CONSTRAIN_1
  325. DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0
  326. DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0
  327. DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1
  328. DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1
  329. DMA_APBPERI_USB_PMS_CONSTRAIN_0
  330. DMA_APBPERI_USB_PMS_CONSTRAIN_0
  331. DMA_APBPERI_USB_PMS_CONSTRAIN_1
  332. DMA_APBPERI_USB_PMS_CONSTRAIN_1
  333. EDMA_BOUNDARY_0
  334. EDMA_BOUNDARY_0
  335. EDMA_BOUNDARY_1
  336. EDMA_BOUNDARY_1
  337. EDMA_BOUNDARY_2
  338. EDMA_BOUNDARY_2
  339. EDMA_BOUNDARY_LOCK
  340. EDMA_BOUNDARY_LOCK
  341. EDMA_PMS_ADC_DAC
  342. EDMA_PMS_ADC_DAC
  343. EDMA_PMS_ADC_DAC_LOCK
  344. EDMA_PMS_ADC_DAC_LOCK
  345. EDMA_PMS_AES
  346. EDMA_PMS_AES
  347. EDMA_PMS_AES_LOCK
  348. EDMA_PMS_AES_LOCK
  349. EDMA_PMS_I2S0
  350. EDMA_PMS_I2S0
  351. EDMA_PMS_I2S0_LOCK
  352. EDMA_PMS_I2S0_LOCK
  353. EDMA_PMS_I2S1
  354. EDMA_PMS_I2S1
  355. EDMA_PMS_I2S1_LOCK
  356. EDMA_PMS_I2S1_LOCK
  357. EDMA_PMS_LCD_CAM
  358. EDMA_PMS_LCD_CAM
  359. EDMA_PMS_LCD_CAM_LOCK
  360. EDMA_PMS_LCD_CAM_LOCK
  361. EDMA_PMS_RMT
  362. EDMA_PMS_RMT
  363. EDMA_PMS_RMT_LOCK
  364. EDMA_PMS_RMT_LOCK
  365. EDMA_PMS_SHA
  366. EDMA_PMS_SHA
  367. EDMA_PMS_SHA_LOCK
  368. EDMA_PMS_SHA_LOCK
  369. EDMA_PMS_SPI2
  370. EDMA_PMS_SPI2
  371. EDMA_PMS_SPI2_LOCK
  372. EDMA_PMS_SPI2_LOCK
  373. EDMA_PMS_SPI3
  374. EDMA_PMS_SPI3
  375. EDMA_PMS_SPI3_LOCK
  376. EDMA_PMS_SPI3_LOCK
  377. EDMA_PMS_UHCI0
  378. EDMA_PMS_UHCI0
  379. EDMA_PMS_UHCI0_LOCK
  380. EDMA_PMS_UHCI0_LOCK
  381. INTERNAL_SRAM_USAGE_0
  382. INTERNAL_SRAM_USAGE_0
  383. INTERNAL_SRAM_USAGE_1
  384. INTERNAL_SRAM_USAGE_1
  385. INTERNAL_SRAM_USAGE_2
  386. INTERNAL_SRAM_USAGE_2
  387. INTERNAL_SRAM_USAGE_3
  388. INTERNAL_SRAM_USAGE_3
  389. INTERNAL_SRAM_USAGE_4
  390. INTERNAL_SRAM_USAGE_4
  391. RETENTION_DISABLE
  392. RETENTION_DISABLE
  393. RTC_PMS
  394. RTC_PMS