Browse Registers In Our Database

Browse below to find the registers you are looking for, or search for one. For each register you can visualize its contents, and for many there is some basic reference information.

Registers in Espressif Systems /ESP32-S3 /WCL

  1. Core_0_ENTRY_10_ADDR
  2. Core_0_ENTRY_10_ADDR
  3. Core_0_ENTRY_11_ADDR
  4. Core_0_ENTRY_11_ADDR
  5. Core_0_ENTRY_12_ADDR
  6. Core_0_ENTRY_12_ADDR
  7. Core_0_ENTRY_13_ADDR
  8. Core_0_ENTRY_13_ADDR
  9. Core_0_ENTRY_1_ADDR
  10. Core_0_ENTRY_1_ADDR
  11. Core_0_ENTRY_2_ADDR
  12. Core_0_ENTRY_2_ADDR
  13. Core_0_ENTRY_3_ADDR
  14. Core_0_ENTRY_3_ADDR
  15. Core_0_ENTRY_4_ADDR
  16. Core_0_ENTRY_4_ADDR
  17. Core_0_ENTRY_5_ADDR
  18. Core_0_ENTRY_5_ADDR
  19. Core_0_ENTRY_6_ADDR
  20. Core_0_ENTRY_6_ADDR
  21. Core_0_ENTRY_7_ADDR
  22. Core_0_ENTRY_7_ADDR
  23. Core_0_ENTRY_8_ADDR
  24. Core_0_ENTRY_8_ADDR
  25. Core_0_ENTRY_9_ADDR
  26. Core_0_ENTRY_9_ADDR
  27. Core_0_ENTRY_CHECK
  28. Core_0_ENTRY_CHECK
  29. Core_0_MESSAGE_ADDR
  30. Core_0_MESSAGE_ADDR
  31. Core_0_MESSAGE_MAX
  32. Core_0_MESSAGE_MAX
  33. Core_0_MESSAGE_PHASE
  34. Core_0_MESSAGE_PHASE
  35. Core_0_NMI_MASK
  36. Core_0_NMI_MASK
  37. Core_0_NMI_MASK_CANCLE
  38. Core_0_NMI_MASK_CANCLE
  39. Core_0_NMI_MASK_DISABLE
  40. Core_0_NMI_MASK_DISABLE
  41. Core_0_NMI_MASK_ENABLE
  42. Core_0_NMI_MASK_ENABLE
  43. Core_0_NMI_MASK_PHASE
  44. Core_0_NMI_MASK_PHASE
  45. Core_0_NMI_MASK_TRIGGER_ADDR
  46. Core_0_NMI_MASK_TRIGGER_ADDR
  47. Core_0_STATUSTABLE1
  48. Core_0_STATUSTABLE1
  49. Core_0_STATUSTABLE10
  50. Core_0_STATUSTABLE10
  51. Core_0_STATUSTABLE11
  52. Core_0_STATUSTABLE11
  53. Core_0_STATUSTABLE12
  54. Core_0_STATUSTABLE12
  55. Core_0_STATUSTABLE13
  56. Core_0_STATUSTABLE13
  57. Core_0_STATUSTABLE2
  58. Core_0_STATUSTABLE2
  59. Core_0_STATUSTABLE3
  60. Core_0_STATUSTABLE3
  61. Core_0_STATUSTABLE4
  62. Core_0_STATUSTABLE4
  63. Core_0_STATUSTABLE5
  64. Core_0_STATUSTABLE5
  65. Core_0_STATUSTABLE6
  66. Core_0_STATUSTABLE6
  67. Core_0_STATUSTABLE7
  68. Core_0_STATUSTABLE7
  69. Core_0_STATUSTABLE8
  70. Core_0_STATUSTABLE8
  71. Core_0_STATUSTABLE9
  72. Core_0_STATUSTABLE9
  73. Core_0_STATUSTABLE_CURRENT
  74. Core_0_STATUSTABLE_CURRENT
  75. Core_0_World_Cancel
  76. Core_0_World_Cancel
  77. Core_0_World_DRam0_PIF
  78. Core_0_World_DRam0_PIF
  79. Core_0_World_IRam0
  80. Core_0_World_IRam0
  81. Core_0_World_Phase
  82. Core_0_World_Phase
  83. Core_0_World_PREPARE
  84. Core_0_World_PREPARE
  85. Core_0_World_TRIGGER_ADDR
  86. Core_0_World_TRIGGER_ADDR
  87. Core_0_World_UPDATE
  88. Core_0_World_UPDATE
  89. Core_1_ENTRY_10_ADDR
  90. Core_1_ENTRY_10_ADDR
  91. Core_1_ENTRY_11_ADDR
  92. Core_1_ENTRY_11_ADDR
  93. Core_1_ENTRY_12_ADDR
  94. Core_1_ENTRY_12_ADDR
  95. Core_1_ENTRY_13_ADDR
  96. Core_1_ENTRY_13_ADDR
  97. Core_1_ENTRY_1_ADDR
  98. Core_1_ENTRY_1_ADDR
  99. Core_1_ENTRY_2_ADDR
  100. Core_1_ENTRY_2_ADDR
  101. Core_1_ENTRY_3_ADDR
  102. Core_1_ENTRY_3_ADDR
  103. Core_1_ENTRY_4_ADDR
  104. Core_1_ENTRY_4_ADDR
  105. Core_1_ENTRY_5_ADDR
  106. Core_1_ENTRY_5_ADDR
  107. Core_1_ENTRY_6_ADDR
  108. Core_1_ENTRY_6_ADDR
  109. Core_1_ENTRY_7_ADDR
  110. Core_1_ENTRY_7_ADDR
  111. Core_1_ENTRY_8_ADDR
  112. Core_1_ENTRY_8_ADDR
  113. Core_1_ENTRY_9_ADDR
  114. Core_1_ENTRY_9_ADDR
  115. Core_1_ENTRY_CHECK
  116. Core_1_ENTRY_CHECK
  117. Core_1_MESSAGE_ADDR
  118. Core_1_MESSAGE_ADDR
  119. Core_1_MESSAGE_MAX
  120. Core_1_MESSAGE_MAX
  121. Core_1_MESSAGE_PHASE
  122. Core_1_MESSAGE_PHASE
  123. Core_1_NMI_MASK
  124. Core_1_NMI_MASK
  125. Core_1_NMI_MASK_CANCLE
  126. Core_1_NMI_MASK_CANCLE
  127. Core_1_NMI_MASK_DISABLE
  128. Core_1_NMI_MASK_DISABLE
  129. Core_1_NMI_MASK_ENABLE
  130. Core_1_NMI_MASK_ENABLE
  131. Core_1_NMI_MASK_PHASE
  132. Core_1_NMI_MASK_PHASE
  133. Core_1_NMI_MASK_TRIGGER_ADDR
  134. Core_1_NMI_MASK_TRIGGER_ADDR
  135. Core_1_STATUSTABLE1
  136. Core_1_STATUSTABLE1
  137. Core_1_STATUSTABLE10
  138. Core_1_STATUSTABLE10
  139. Core_1_STATUSTABLE11
  140. Core_1_STATUSTABLE11
  141. Core_1_STATUSTABLE12
  142. Core_1_STATUSTABLE12
  143. Core_1_STATUSTABLE13
  144. Core_1_STATUSTABLE13
  145. Core_1_STATUSTABLE2
  146. Core_1_STATUSTABLE2
  147. Core_1_STATUSTABLE3
  148. Core_1_STATUSTABLE3
  149. Core_1_STATUSTABLE4
  150. Core_1_STATUSTABLE4
  151. Core_1_STATUSTABLE5
  152. Core_1_STATUSTABLE5
  153. Core_1_STATUSTABLE6
  154. Core_1_STATUSTABLE6
  155. Core_1_STATUSTABLE7
  156. Core_1_STATUSTABLE7
  157. Core_1_STATUSTABLE8
  158. Core_1_STATUSTABLE8
  159. Core_1_STATUSTABLE9
  160. Core_1_STATUSTABLE9
  161. Core_1_STATUSTABLE_CURRENT
  162. Core_1_STATUSTABLE_CURRENT
  163. Core_1_World_Cancel
  164. Core_1_World_Cancel
  165. Core_1_World_DRam0_PIF
  166. Core_1_World_DRam0_PIF
  167. Core_1_World_IRam0
  168. Core_1_World_IRam0
  169. Core_1_World_Phase
  170. Core_1_World_Phase
  171. Core_1_World_PREPARE
  172. Core_1_World_PREPARE
  173. Core_1_World_TRIGGER_ADDR
  174. Core_1_World_TRIGGER_ADDR
  175. Core_1_World_UPDATE
  176. Core_1_World_UPDATE