Regviz

Browse Registers In Our Database

Browse below to find the registers you are looking for, or search for one. For each register you can visualize its contents, and for many there is some basic reference information.

Registers in NXP Semiconductors /LPC43xx /SGPIO

  1. CLR_EN_0
  2. CLR_EN_1
  3. CLR_EN_2
  4. CLR_EN_3
  5. CLR_STATUS_0
  6. CLR_STATUS_1
  7. CLR_STATUS_2
  8. CLR_STATUS_3
  9. COUNT[0]
  10. COUNT[1]
  11. COUNT[10]
  12. COUNT[11]
  13. COUNT[12]
  14. COUNT[13]
  15. COUNT[14]
  16. COUNT[15]
  17. COUNT[2]
  18. COUNT[3]
  19. COUNT[4]
  20. COUNT[5]
  21. COUNT[6]
  22. COUNT[7]
  23. COUNT[8]
  24. COUNT[9]
  25. CTRL_DISABLE
  26. CTRL_ENABLE
  27. ENABLE_0
  28. ENABLE_1
  29. ENABLE_2
  30. ENABLE_3
  31. GPIO_INREG
  32. GPIO_OENREG
  33. GPIO_OUTREG
  34. MASK_A
  35. MASK_H
  36. MASK_I
  37. MASK_P
  38. OUT_MUX_CFG[0]
  39. OUT_MUX_CFG[1]
  40. OUT_MUX_CFG[10]
  41. OUT_MUX_CFG[11]
  42. OUT_MUX_CFG[12]
  43. OUT_MUX_CFG[13]
  44. OUT_MUX_CFG[14]
  45. OUT_MUX_CFG[15]
  46. OUT_MUX_CFG[2]
  47. OUT_MUX_CFG[3]
  48. OUT_MUX_CFG[4]
  49. OUT_MUX_CFG[5]
  50. OUT_MUX_CFG[6]
  51. OUT_MUX_CFG[7]
  52. OUT_MUX_CFG[8]
  53. OUT_MUX_CFG[9]
  54. POS[0]
  55. POS[1]
  56. POS[10]
  57. POS[11]
  58. POS[12]
  59. POS[13]
  60. POS[14]
  61. POS[15]
  62. POS[2]
  63. POS[3]
  64. POS[4]
  65. POS[5]
  66. POS[6]
  67. POS[7]
  68. POS[8]
  69. POS[9]
  70. PRESET[0]
  71. PRESET[1]
  72. PRESET[10]
  73. PRESET[11]
  74. PRESET[12]
  75. PRESET[13]
  76. PRESET[14]
  77. PRESET[15]
  78. PRESET[2]
  79. PRESET[3]
  80. PRESET[4]
  81. PRESET[5]
  82. PRESET[6]
  83. PRESET[7]
  84. PRESET[8]
  85. PRESET[9]
  86. REG[0]
  87. REG[1]
  88. REG[10]
  89. REG[11]
  90. REG[12]
  91. REG[13]
  92. REG[14]
  93. REG[15]
  94. REG[2]
  95. REG[3]
  96. REG[4]
  97. REG[5]
  98. REG[6]
  99. REG[7]
  100. REG[8]
  101. REG[9]
  102. REG_SS[0]
  103. REG_SS[1]
  104. REG_SS[10]
  105. REG_SS[11]
  106. REG_SS[12]
  107. REG_SS[13]
  108. REG_SS[14]
  109. REG_SS[15]
  110. REG_SS[2]
  111. REG_SS[3]
  112. REG_SS[4]
  113. REG_SS[5]
  114. REG_SS[6]
  115. REG_SS[7]
  116. REG_SS[8]
  117. REG_SS[9]
  118. SET_EN_0
  119. SET_EN_1
  120. SET_EN_2
  121. SET_EN_3
  122. SET_STATUS_0
  123. SET_STATUS_1
  124. SET_STATUS_2
  125. SET_STATUS_3
  126. SGPIO_MUX_CFG[0]
  127. SGPIO_MUX_CFG[1]
  128. SGPIO_MUX_CFG[10]
  129. SGPIO_MUX_CFG[11]
  130. SGPIO_MUX_CFG[12]
  131. SGPIO_MUX_CFG[13]
  132. SGPIO_MUX_CFG[14]
  133. SGPIO_MUX_CFG[15]
  134. SGPIO_MUX_CFG[2]
  135. SGPIO_MUX_CFG[3]
  136. SGPIO_MUX_CFG[4]
  137. SGPIO_MUX_CFG[5]
  138. SGPIO_MUX_CFG[6]
  139. SGPIO_MUX_CFG[7]
  140. SGPIO_MUX_CFG[8]
  141. SGPIO_MUX_CFG[9]
  142. SLICE_MUX_CFG[0]
  143. SLICE_MUX_CFG[1]
  144. SLICE_MUX_CFG[10]
  145. SLICE_MUX_CFG[11]
  146. SLICE_MUX_CFG[12]
  147. SLICE_MUX_CFG[13]
  148. SLICE_MUX_CFG[14]
  149. SLICE_MUX_CFG[15]
  150. SLICE_MUX_CFG[2]
  151. SLICE_MUX_CFG[3]
  152. SLICE_MUX_CFG[4]
  153. SLICE_MUX_CFG[5]
  154. SLICE_MUX_CFG[6]
  155. SLICE_MUX_CFG[7]
  156. SLICE_MUX_CFG[8]
  157. SLICE_MUX_CFG[9]
  158. STATUS_0
  159. STATUS_1
  160. STATUS_2
  161. STATUS_3