Regviz

Allwinner /D1H /CSIC /CSIC_DMA0 /CSIC_DMA_VI_TO_TH0_REG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CSIC_DMA_VI_TO_TH0_REG

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Allwinner/D1H/CSIC/CSIC_DMA1/CSIC_DMA_VI_TO_TH0_REG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Description

CSIC DMA Video Input Timeout Threshold0 Register

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data