Allwinner /D1H /SPI0 /SPI_BATC

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Interpret as SPI_BATC

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (byte_aligned)wms0 (SS0)ss_sel 0 (high)spol 0 (SPI_controller)ss_owner 0 (low)ss_level 0tx_frm_len0rx_frm_len0 (disable)tbc_int_en 0 (busy)tbc 0 (delay)msms 0 (idle)tce

tbc=busy, ss_level=low, msms=delay, tbc_int_en=disable, spol=high, ss_sel=SS0, wms=byte_aligned, tce=idle, ss_owner=SPI_controller

Description

SPI Bit-Aligned Transfer Configure Register

Fields

wms

Work Mode Select

0 (byte_aligned): undefined

1 (reserved): undefined

2 (bit_aligned_3wire): undefined

3 (bit_aligned_standard): undefined

ss_sel

SPI Chip Select

0 (SS0): undefined

1 (SS1): undefined

2 (SS2): undefined

3 (SS3): undefined

spol

SPI Chip Select Signal Polarity Control

0 (high): undefined

1 (low): undefined

ss_owner

SS Output Owner Select

0 (SPI_controller): undefined

1 (Software): undefined

ss_level

0 (low): undefined

1 (high): undefined

tx_frm_len

Configure the length of serial data frame of TX

rx_frm_len

Configure the length of serial data frame of RX

tbc_int_en

Transfer Bits Completed Interrupt Enable

0 (disable): undefined

1 (enable): undefined

tbc

Transfer Bits Completed

0 (busy): undefined

1 (completed): undefined

msms

Master Sample Standard

0 (delay): undefined

1 (standard): undefined

tce

Transfer Control Enable

0 (idle): undefined

1 (init): undefined

Links

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