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Allwinner /D1H /SPI0 /SPI_BCC

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Interpret as SPI_BCC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0stc0dbc0 (single)drm 0 (disable)quad_en

quad_en=disable, drm=single

Description

SPI Master Burst Control Register

Fields

stc

Master Single Mode Transmit Counter
dbc

Master Dummy Burst Counter
drm

Master Dual Mode RX Enable

0 (single): undefined

1 (dual): undefined
quad_en

Quad Mode Enable

0 (disable): undefined

1 (enable): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data