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Allwinner /D1H /SPI0 /SPI_FCR

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Interpret as SPI_FCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0rf_trig_level0 (disable)rf_drq_en 0 (disable)rf_test_en 0 (rf_rst)rf_rst 0tf_trig_level0 (disable)tf_drq_en 0 (disable)tf_test_en 0 (tf_rst)tf_rst

tf_test_en=disable, rf_drq_en=disable, tf_drq_en=disable, rf_test_en=disable

Description

SPI FIFO Control Register

Fields

rf_trig_level

RXFIFO Ready Request Trigger Level
rf_drq_en

RXFIFO DMA Request Enable

0 (disable): undefined

1 (enable): undefined
rf_test_en

RXFIFO Test Mode Enable

0 (disable): undefined

1 (enable): undefined
rf_rst

RXFIFO Reset
tf_trig_level

TXFIFO Empty Request Trigger Level
tf_drq_en

TXFIFO DMA Request Enable

0 (disable): undefined

1 (enable): undefined
tf_test_en

TXFIFO Test Mode Enable

0 (disable): undefined

1 (enable): undefined
tf_rst

TXFIFO Reset

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data