Allwinner /D1H /SPI0 /SPI_GCR

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Interpret as SPI_GCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)en 0 (slave)mode 0 (old_mode)mode_selec 0 (normal)tp_en 0 (srst)srst

mode=slave, tp_en=normal, en=disable, mode_selec=old_mode

Description

SPI Global Control Register

Fields

en

SPI Module Enable Control

0 (disable): undefined

1 (enable): undefined

mode

SPI Function Mode Select

0 (slave): undefined

1 (master): undefined

mode_selec

Sample timing Mode Select

0 (old_mode): Old mode of Sample Timing

1 (new_mode): New mode of Sample Timing

tp_en

Transmit Pause Enable

0 (normal): normal operation, ignore RXFIFO status

1 (stop_when_full): Stop transmit data when RXFIFO full

srst

Soft reset

Links

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