rf_emp=not_empty, tf_ovf=not_overflow, tf_emp=not_empty, tf_full=not_full, tc=busy, rf_udr=not_underrun, rf_ovf=not_overflow, tf_udr=not_underrun, rf_full=not_full
SPI Interrupt Status Register
| rf_rdy | RXFIFO Ready |
| rf_emp | RXFIFO Empty 0 (not_empty): undefined 1 (empty): undefined |
| rf_full | RXFIFO Full 0 (not_full): undefined 1 (full): undefined |
| tf_ready | TXFIFO Ready |
| tf_emp | TXFIFO Empty 0 (not_empty): undefined 1 (empty): undefined |
| tf_full | TXFIFO Full 0 (not_full): undefined 1 (full): undefined |
| rf_ovf | RXFIFO Overflow 0 (not_overflow): undefined 1 (overflow): undefined |
| rf_udr | RXFIFO Underrun 0 (not_underrun): undefined 1 (underrun): undefined |
| tf_ovf | TXFIFO Overflow 0 (not_overflow): undefined 1 (overflow): undefined |
| tf_udr | TXFIFO Underrun 0 (not_underrun): undefined 1 (underrun): undefined |
| tc | Transfer Completed 0 (busy): undefined 1 (transfer_completed): undefined |
| ssi | SS Invalid Enable |