Allwinner /D1H /SPI0 /SPI_ISR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SPI_ISR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (rf_rdy)rf_rdy 0 (not_empty)rf_emp 0 (not_full)rf_full 0 (tf_ready)tf_ready 0 (not_empty)tf_emp 0 (not_full)tf_full 0 (not_overflow)rf_ovf 0 (not_underrun)rf_udr 0 (not_overflow)tf_ovf 0 (not_underrun)tf_udr 0 (busy)tc 0 (ssi)ssi

tc=busy, rf_full=not_full, tf_udr=not_underrun, tf_ovf=not_overflow, rf_udr=not_underrun, rf_ovf=not_overflow, rf_emp=not_empty, tf_full=not_full, tf_emp=not_empty

Description

SPI Interrupt Status Register

Fields

rf_rdy

RXFIFO Ready

rf_emp

RXFIFO Empty

0 (not_empty): undefined

1 (empty): undefined

rf_full

RXFIFO Full

0 (not_full): undefined

1 (full): undefined

tf_ready

TXFIFO Ready

tf_emp

TXFIFO Empty

0 (not_empty): undefined

1 (empty): undefined

tf_full

TXFIFO Full

0 (not_full): undefined

1 (full): undefined

rf_ovf

RXFIFO Overflow

0 (not_overflow): undefined

1 (overflow): undefined

rf_udr

RXFIFO Underrun

0 (not_underrun): undefined

1 (underrun): undefined

tf_ovf

TXFIFO Overflow

0 (not_overflow): undefined

1 (overflow): undefined

tf_udr

TXFIFO Underrun

0 (not_underrun): undefined

1 (underrun): undefined

tc

Transfer Completed

0 (busy): undefined

1 (transfer_completed): undefined

ssi

SS Invalid Enable

Links

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