cpha=P0, sdm=delay, ss_sel=ss0, ssctl=assert, sdc=normal, sdc1=normal, dhb=receive, ddb=zero, rpsm=normal, sddm=normal, spol=high, ss_level=low, ss_owner=spi_controller, xch=idle, cpol=high, fbs=msb
SPI Transfer Control Register
| cpha | SPI Clock/Data Phase Control 0 (P0): Phase 0 (Leading edge for sample data) 1 (P1): Phase 1 (Leading edge for setup data) |
| cpol | SPI Clock Polarity Control 0 (high): Active high polarity 1 (low): Active low polarity |
| spol | SPI Chip Select Signal Polarity Control 0 (high): Active high polarity 1 (low): Active low polarity |
| ssctl | 0 (assert): SPI_SSx remains asserted between SPI bursts 1 (negate): Negate SPI_SSx between SPI bursts |
| ss_sel | 0 (ss0): undefined 1 (ss1): undefined 2 (ss2): undefined 3 (ss3): undefined |
| ss_owner | 0 (spi_controller): undefined 1 (software): undefined |
| ss_level | 0 (low): undefined 1 (high): undefined |
| dhb | Discard Hash Burst 0 (receive): Receiving all SPI bursts in the BC period 1 (discard): Discard unused SPI bursts |
| ddb | Dummy Burst Type 0 (zero): The bit value of dummy SPI burst is zero 1 (one): The bit value of dummy SPI burst is one |
| rpsm | Rapids Mode Select 0 (normal): Normal write mode 1 (rapid): Rapid write mode |
| sdc | Master Sample Data Control 0 (normal): Normal operation, do not delay the internal read sample point 1 (delay): Delay the internal read sample point |
| fbs | First Transmit Bit Select 0 (msb): MSB first 1 (lsb): LSB first |
| sdm | Master Sample Data Mode 0 (delay): delay sample mode 1 (normal): normal sample mode |
| sddm | Sending Data Delay Mode 0 (normal): normal sending 1 (delay): delay sending |
| sdc1 | Master Sample Data Control register1 0 (normal): normal operation, do not delay the internal read sample point 1 (delay): delay the internal read sample point |
| xch | Exchange Burst 0 (idle): undefined 1 (initiate_exchange): undefined |