Allwinner /D1H /SPI0 /SPI_TCR

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Interpret as SPI_TCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (P0)cpha 0 (high)cpol 0 (high)spol 0 (assert)ssctl 0 (ss0)ss_sel 0 (spi_controller)ss_owner 0 (low)ss_level 0 (receive)dhb 0 (zero)ddb 0 (normal)rpsm 0 (normal)sdc 0 (msb)fbs 0 (delay)sdm 0 (normal)sddm 0 (normal)sdc1 0 (idle)xch

dhb=receive, rpsm=normal, spol=high, ss_sel=ss0, ss_owner=spi_controller, cpol=high, ssctl=assert, xch=idle, sdc1=normal, ddb=zero, sddm=normal, sdc=normal, ss_level=low, cpha=P0, fbs=msb, sdm=delay

Description

SPI Transfer Control Register

Fields

cpha

SPI Clock/Data Phase Control

0 (P0): Phase 0 (Leading edge for sample data)

1 (P1): Phase 1 (Leading edge for setup data)

cpol

SPI Clock Polarity Control

0 (high): Active high polarity

1 (low): Active low polarity

spol

SPI Chip Select Signal Polarity Control

0 (high): Active high polarity

1 (low): Active low polarity

ssctl

0 (assert): SPI_SSx remains asserted between SPI bursts

1 (negate): Negate SPI_SSx between SPI bursts

ss_sel

0 (ss0): undefined

1 (ss1): undefined

2 (ss2): undefined

3 (ss3): undefined

ss_owner

0 (spi_controller): undefined

1 (software): undefined

ss_level

0 (low): undefined

1 (high): undefined

dhb

Discard Hash Burst

0 (receive): Receiving all SPI bursts in the BC period

1 (discard): Discard unused SPI bursts

ddb

Dummy Burst Type

0 (zero): The bit value of dummy SPI burst is zero

1 (one): The bit value of dummy SPI burst is one

rpsm

Rapids Mode Select

0 (normal): Normal write mode

1 (rapid): Rapid write mode

sdc

Master Sample Data Control

0 (normal): Normal operation, do not delay the internal read sample point

1 (delay): Delay the internal read sample point

fbs

First Transmit Bit Select

0 (msb): MSB first

1 (lsb): LSB first

sdm

Master Sample Data Mode

0 (delay): delay sample mode

1 (normal): normal sample mode

sddm

Sending Data Delay Mode

0 (normal): normal sending

1 (delay): delay sending

sdc1

Master Sample Data Control register1

0 (normal): normal operation, do not delay the internal read sample point

1 (delay): delay the internal read sample point

xch

Exchange Burst

0 (idle): undefined

1 (initiate_exchange): undefined

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