Atmel /AT91SAM9CN12 /DDRSDRC /TPR0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TPR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TRAS0TRCD0TWR0TRC0TRP0TRRD0TWTR0 (REDUCE_WRRD)REDUCE_WRRD 0TMRD

Description

DDRSDRC Timing Parameter 0 Register

Fields

TRAS

Active to Precharge Delay

TRCD

Row to Column Delay

TWR

Write Recovery Delay

TRC

Row Cycle Delay

TRP

Row Precharge Delay

TRRD

Active bankA to Active bankB

TWTR

Internal Write to Read Delay

REDUCE_WRRD

Reduce Write to Read Delay

TMRD

Load Mode Register Command to Active or Refresh Command

Links

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