Atmel /AT91SAM9CN12 /DMAC /CTRLB0

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Interpret as CTRLB0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AHB_IF0)SIF0 (AHB_IF0)DIF0 (DISABLE)SRC_PIP 0 (DISABLE)DST_PIP 0 (FETCH_FROM_MEM)SRC_DSCR 0 (FETCH_FROM_MEM)DST_DSCR 0 (MEM2MEM_DMA_FC)FC0 (INCREMENTING)SRC_INCR 0 (INCREMENTING)DST_INCR 0 (IEN)IEN 0 (DISABLE)AUTO

DST_DSCR=FETCH_FROM_MEM, FC=MEM2MEM_DMA_FC, DST_INCR=INCREMENTING, SIF=AHB_IF0, AUTO=DISABLE, SRC_INCR=INCREMENTING, DST_PIP=DISABLE, SRC_PIP=DISABLE, SRC_DSCR=FETCH_FROM_MEM, DIF=AHB_IF0

Description

DMAC Channel Control B Register (ch_num = 0)

Fields

SIF

Source Interface Selection Field

0 (AHB_IF0): The source transfer is done via AHB-Lite Interface 0

1 (AHB_IF1): The source transfer is done via AHB-Lite Interface 1

DIF

Destination Interface Selection Field

0 (AHB_IF0): The destination transfer is done via AHB-Lite Interface 0

1 (AHB_IF1): The destination transfer is done via AHB-Lite Interface 1

SRC_PIP

Source Picture-in-Picture Mode

0 (DISABLE): Picture-in-Picture mode is disabled. The source data area is contiguous.

1 (ENABLE): Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount.

DST_PIP

Destination Picture-in-Picture Mode

0 (DISABLE): Picture-in-Picture mode is disabled. The Destination data area is contiguous.

1 (ENABLE): Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount.

SRC_DSCR

Source Address Descriptor

0 (FETCH_FROM_MEM): Source address is updated when the descriptor is fetched from the memory.

1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the source.

DST_DSCR

Destination Address Descriptor

0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory.

1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination.

FC

Flow Control

0 (MEM2MEM_DMA_FC): Memory-to-Memory Transfer DMAC is flow controller

1 (MEM2PER_DMA_FC): Memory-to-Peripheral Transfer DMAC is flow controller

2 (PER2MEM_DMA_FC): Peripheral-to-Memory Transfer DMAC is flow controller

3 (PER2PER_DMA_FC): Peripheral-to-Peripheral Transfer DMAC is flow controller

SRC_INCR

Incrementing, Decrementing or Fixed Address for the Source

0 (INCREMENTING): The source address is incremented

1 (DECREMENTING): The source address is decremented

2 (FIXED): The source address remains unchanged

DST_INCR

Incrementing, Decrementing or Fixed Address for the Destination

0 (INCREMENTING): The destination address is incremented

1 (DECREMENTING): The destination address is decremented

2 (FIXED): The destination address remains unchanged

IEN
AUTO

Automatic Multiple Buffer Transfer

0 (DISABLE): Automatic multiple buffer transfer is disabled.

1 (ENABLE): Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred.

Links

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