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Atmel /AT91SAM9G15 /DMAC1 /DADDR2

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Interpret as DADDR2

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https://regviz.com/r/Atmel/AT91SAM9G25/DMAC1/DADDR2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DADDR

Description

DMAC Channel Destination Address Register (ch_num = 2)

Fields

DADDR

Channel x Destination Address

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data