Atmel /AT91SAM9G15 /LCDC /HEOIDR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as HEOIDR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA)DMA 0 (DSCR)DSCR 0 (ADD)ADD 0 (DONE)DONE 0 (OVR)OVR 0 (UDMA)UDMA 0 (UDSCR)UDSCR 0 (UADD)UADD 0 (UDONE)UDONE 0 (UOVR)UOVR 0 (VDMA)VDMA 0 (VDSCR)VDSCR 0 (VADD)VADD 0 (VDONE)VDONE 0 (VOVR)VOVR

Description

High End Overlay Interrupt Disable Register

Fields

DMA

End of DMA Transfer Interrupt Disable Register

DSCR

Descriptor Loaded Interrupt Disable Register

ADD

Head Descriptor Loaded Interrupt Disable Register

DONE

End of List Interrupt Disable Register

OVR

Overflow Interrupt Disable Register

UDMA

End of DMA Transfer for U or UV Chrominance Component Interrupt Disable Register

UDSCR

Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register

UADD

Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register

UDONE

End of List Interrupt for U or UV Chrominance Component Disable Register

UOVR

Overflow Interrupt for U or UV Chrominance Component Disable Register

VDMA

End of DMA Transfer for V Chrominance Component Interrupt Disable Register

VDSCR

Descriptor Loaded for V Chrominance Component Interrupt Disable Register

VADD

Head Descriptor Loaded for V Chrominance Component Interrupt Disable Register

VDONE

End of List for V Chrominance Component Interrupt Disable Register

VOVR

Overflow for V Chrominance Component Interrupt Disable Register

Links

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