PREB=MCK, DIVA=CLK_OFF, DIVB=CLK_OFF, PREA=MCK
PWM Mode Register
| DIVA | CLKA, CLKB Divide Factor 0 (CLK_OFF): CLKA, CLKB clock is turned off 1 (CLK_DIV1): CLKA, CLKB clock is clock selected by PREA, PREB |
| PREA | 0 (MCK): Master Clock 1 (MCKDIV2): Master Clock divided by 2 2 (MCKDIV4): Master Clock divided by 4 3 (MCKDIV8): Master Clock divided by 8 4 (MCKDIV16): Master Clock divided by 16 5 (MCKDIV32): Master Clock divided by 32 6 (MCKDIV64): Master Clock divided by 64 7 (MCKDIV128): Master Clock divided by 128 8 (MCKDIV256): Master Clock divided by 256 9 (MCKDIV512): Master Clock divided by 512 10 (MCKDIV1024): Master Clock divided by 1024 |
| DIVB | CLKA, CLKB Divide Factor 0 (CLK_OFF): CLKA, CLKB clock is turned off 1 (CLK_DIV1): CLKA, CLKB clock is clock selected by PREA, PREB |
| PREB | 0 (MCK): Master Clock 1 (MCKDIV2): Master Clock divided by 2 2 (MCKDIV4): Master Clock divided by 4 3 (MCKDIV8): Master Clock divided by 8 4 (MCKDIV16): Master Clock divided by 16 5 (MCKDIV32): Master Clock divided by 32 6 (MCKDIV64): Master Clock divided by 64 7 (MCKDIV128): Master Clock divided by 128 8 (MCKDIV256): Master Clock divided by 256 9 (MCKDIV512): Master Clock divided by 512 10 (MCKDIV1024): Master Clock divided by 1024 |