Regviz

Atmel /AT91SAM9G35 /DBGU /BRGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as BRGR

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https://regviz.com/r/Atmel/AT91SAM9G20/DBGU/BRGR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)CD

CD=DISABLED

Description

Baud Rate Generator Register

Fields

CD

Clock Divisor

0 (DISABLED): DBGU Disabled

1 (MCK): MCK

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data