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Atmel /AT91SAM9G35 /HSMCI1 /MR

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Interpret as MR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIV0PWSDIV 0 (RDPROOF)RDPROOF 0 (WRPROOF)WRPROOF 0 (FBYTE)FBYTE 0 (PADV)PADV 0 (CLKODD)CLKODD

Description

Mode Register

Fields

CLKDIV

Clock Divider
PWSDIV

Power Saving Divider
RDPROOF

Read Proof Enable
WRPROOF

Write Proof Enable
FBYTE

Force Byte Transfer
PADV

Padding Value
CLKODD

Clock divider is odd

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data