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Atmel /AT91SAM9M10 /DDRSDRC1 /TPR2

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Interpret as TPR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TXARD0TXARDS0TRPA0TRTP

Description

DDRSDRC Timing Parameter 2 Register

Fields

TXARD

Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.
TXARDS

Exit Active Power Down Delay to Read Command in Mode “Slow Exit”.
TRPA

Row Precharge All Delay
TRTP

Read to Precharge

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data