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Atmel /AT91SAM9M10 /DMAC /CHSR

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Interpret as CHSR

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https://regviz.com/r/Atmel/AT91SAM9M11/DMAC/CHSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENA0)ENA0 0 (ENA1)ENA1 0 (ENA2)ENA2 0 (ENA3)ENA3 0 (ENA4)ENA4 0 (ENA5)ENA5 0 (ENA6)ENA6 0 (ENA7)ENA7 0 (SUSP0)SUSP0 0 (SUSP1)SUSP1 0 (SUSP2)SUSP2 0 (SUSP3)SUSP3 0 (SUSP4)SUSP4 0 (SUSP5)SUSP5 0 (SUSP6)SUSP6 0 (SUSP7)SUSP7 0 (EMPT0)EMPT0 0 (EMPT1)EMPT1 0 (EMPT2)EMPT2 0 (EMPT3)EMPT3 0 (EMPT4)EMPT4 0 (EMPT5)EMPT5 0 (EMPT6)EMPT6 0 (EMPT7)EMPT7 0 (STAL0)STAL0 0 (STAL1)STAL1 0 (STAL2)STAL2 0 (STAL3)STAL3 0 (STAL4)STAL4 0 (STAL5)STAL5 0 (STAL6)STAL6 0 (STAL7)STAL7

Description

DMAC Channel Handler Status Register

Fields

ENA0

[7:0]
ENA1

[7:0]
ENA2

[7:0]
ENA3

[7:0]
ENA4

[7:0]
ENA5

[7:0]
ENA6

[7:0]
ENA7

[7:0]
SUSP0

[7:0]
SUSP1

[7:0]
SUSP2

[7:0]
SUSP3

[7:0]
SUSP4

[7:0]
SUSP5

[7:0]
SUSP6

[7:0]
SUSP7

[7:0]
EMPT0

[7:0]
EMPT1

[7:0]
EMPT2

[7:0]
EMPT3

[7:0]
EMPT4

[7:0]
EMPT5

[7:0]
EMPT6

[7:0]
EMPT7

[7:0]
STAL0

[7:0]
STAL1

[7:0]
STAL2

[7:0]
STAL3

[7:0]
STAL4

[7:0]
STAL5

[7:0]
STAL6

[7:0]
STAL7

[7:0]

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data