Atmel /AT91SAM9M10 /DMAC /CTRLA5

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Interpret as CTRLA5

SCSIZE=CHK_1, SRC_WIDTH=BYTE, DST_WIDTH=BYTE, DCSIZE=CHK_1

Description

DMAC Channel Control A Register (ch_num = 5)

Fields

BTSIZE
SCSIZE	0 (CHK_1): 1 data transferred 1 (CHK_4): 4 data transferred 2 (CHK_8): 8 data transferred 3 (CHK_16): 16 data transferred 4 (CHK_32): 32 data transferred 5 (CHK_64): 64 data transferred 6 (CHK_128): 128 data transferred 7 (CHK_256): 256 data transferred
DCSIZE	0 (CHK_1): 1 data transferred 1 (CHK_4): 4 data transferred 2 (CHK_8): 8 data transferred 3 (CHK_16): 16 data transferred 4 (CHK_32): 32 data transferred 5 (CHK_64): 64 data transferred 6 (CHK_128): 128 data transferred 7 (CHK_256): 256 data transferred
SRC_WIDTH	0 (BYTE): the transfer size is set to 8-bit width 1 (HALF_WORD): the transfer size is set to 16-bit width 2 (WORD): the transfer size is set to 32-bit width
DST_WIDTH	0 (BYTE): the transfer size is set to 8-bit width 1 (HALF_WORD): the transfer size is set to 16-bit width 2 (WORD): the transfer size is set to 32-bit width
DONE

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