DST_INCR=INCREMENTING, SRC_INCR=INCREMENTING, DIF=AHB_IFO, FC=MEM2MEM_DMA_FC, SIF=AHB_IFO
DMAC Channel Control B Register (ch_num = 4)
| SIF | Source Interface Selection Field 0 (AHB_IFO): The source transfer is done via AHB-Lite Interface 0 1 (AHB_IF1): The source transfer is done via AHB-Lite Interface 1 2 (AHB_IF2): The source transfer is done via AHB-Lite Interface 2 |
| DIF | Destination Interface Selection Field 0 (AHB_IFO): The destination transfer is done via AHB-Lite Interface 0 1 (AHB_IF1): The destination transfer is done via AHB-Lite Interface 1 2 (AHB_IF2): The destination transfer is done via AHB-Lite Interface 2 |
| SRC_DSCR | |
| DST_DSCR | |
| FC | 0 (MEM2MEM_DMA_FC): Memory-to-Memory Transfer DMAC is flow controller 1 (MEM2PER_DMA_FC): Memory-to-Peripheral Transfer DMAC is flow controller 2 (PER2MEM_DMA_FC): Peripheral-to-Memory Transfer DMAC is flow controller 3 (PER2PER_DMA_FC): Peripheral-to-Peripheral Transfer DMAC is flow controller 4 (PER2MEM_PER_FC): Peripheral-to-Memory Transfer DMAC is flow controller 5 (MEM2PER_PER_FC): Memory-to-Peripheral Transfer DMAC is flow controller 6 (PER2PER_SPER_FC): Peripheral-to-Peripheral Transfer DMAC is flow controller 7 (PER2PER_DPER_FC): Peripheral-to-Peripheral Transfer DMAC is flow controller |
| SRC_INCR | 0 (INCREMENTING): The source address is incremented 1 (DECREMENTING): The source address is decremented 2 (FIXED): The source address remains unchanged |
| DST_INCR | 0 (INCREMENTING): The destination address is incremented 1 (DECREMENTING): The destination address is decremented 2 (FIXED): The destination address remains unchanged |
| IEN | |
| AUTO |