LDRB=NONE, LDRA=NONE, ETRGEDG=NONE, BURST=NONE, TCCLKS=TIMER_CLOCK1
Channel Mode Register (channel = 0)
| TCCLKS | Clock Selection 0 (TIMER_CLOCK1): Clock selected: TCLK1 1 (TIMER_CLOCK2): Clock selected: TCLK2 2 (TIMER_CLOCK3): Clock selected: TCLK3 3 (TIMER_CLOCK4): Clock selected: TCLK4 4 (TIMER_CLOCK5): Clock selected: TCLK5 5 (XC0): Clock selected: XC0 6 (XC1): Clock selected: XC1 7 (XC2): Clock selected: XC2 |
| CLKI | Clock Invert |
| BURST | Burst Signal Selection 0 (NONE): The clock is not gated by an external signal. 1 (XC0): XC0 is ANDed with the selected clock. 2 (XC1): XC1 is ANDed with the selected clock. 3 (XC2): XC2 is ANDed with the selected clock. |
| LDBSTOP | Counter Clock Stopped with RB Loading |
| LDBDIS | Counter Clock Disable with RB Loading |
| ETRGEDG | External Trigger Edge Selection 0 (NONE): The clock is not gated by an external signal. 1 (RISING): Rising edge 2 (FALLING): Falling edge 3 (EDGE): Each edge |
| ABETRG | TIOA or TIOB External Trigger Selection |
| CPCTRG | RC Compare Trigger Enable |
| WAVE | |
| LDRA | RA Loading Selection 0 (NONE): None 1 (RISING): Rising edge of TIOA 2 (FALLING): Falling edge of TIOA 3 (EDGE): Each edge of TIOA |
| LDRB | RB Loading Selection 0 (NONE): None 1 (RISING): Rising edge of TIOA 2 (FALLING): Falling edge of TIOA 3 (EDGE): Each edge of TIOA |