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Atmel /AT91SAM9N12 /DBGU /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RSTRX)RSTRX 0 (RSTTX)RSTTX 0 (RXEN)RXEN 0 (RXDIS)RXDIS 0 (TXEN)TXEN 0 (TXDIS)TXDIS 0 (RSTSTA)RSTSTA

Description

Control Register

Fields

RSTRX

Reset Receiver
RSTTX

Reset Transmitter
RXEN

Receiver Enable
RXDIS

Receiver Disable
TXEN

Transmitter Enable
TXDIS

Transmitter Disable
RSTSTA

Reset Status Bits

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data