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Atmel /AT91SAM9N12 /DMAC /CHDR

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Interpret as CHDR

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https://regviz.com/r/Atmel/AT91SAM9G25/DMAC1/CHDR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DIS0)DIS0 0 (DIS1)DIS1 0 (DIS2)DIS2 0 (DIS3)DIS3 0 (DIS4)DIS4 0 (DIS5)DIS5 0 (DIS6)DIS6 0 (DIS7)DIS7 0 (RES0)RES0 0 (RES1)RES1 0 (RES2)RES2 0 (RES3)RES3 0 (RES4)RES4 0 (RES5)RES5 0 (RES6)RES6 0 (RES7)RES7

Description

DMAC Channel Handler Disable Register

Fields

DIS0

Disable [7:0]
DIS1

Disable [7:0]
DIS2

Disable [7:0]
DIS3

Disable [7:0]
DIS4

Disable [7:0]
DIS5

Disable [7:0]
DIS6

Disable [7:0]
DIS7

Disable [7:0]
RES0

Resume [7:0]
RES1

Resume [7:0]
RES2

Resume [7:0]
RES3

Resume [7:0]
RES4

Resume [7:0]
RES5

Resume [7:0]
RES6

Resume [7:0]
RES7

Resume [7:0]

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data