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Atmel /AT91SAM9N12 /DMAC /CTRLA2

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Interpret as CTRLA2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BTSIZE0 (CHK_1)SCSIZE 0 (CHK_1)DCSIZE 0 (BYTE)SRC_WIDTH 0 (BYTE)DST_WIDTH 0 (DONE)DONE

DST_WIDTH=BYTE, DCSIZE=CHK_1, SRC_WIDTH=BYTE, SCSIZE=CHK_1

Description

DMAC Channel Control A Register (ch_num = 2)

Fields

BTSIZE

Buffer Transfer Size
SCSIZE

Source Chunk Transfer Size.

0 (CHK_1): 1 data transferred

1 (CHK_4): 4 data transferred

2 (CHK_8): 8 data transferred

3 (CHK_16): 16 data transferred

4 (CHK_32): 32 data transferred

5 (CHK_64): 64 data transferred

6 (CHK_128): 128 data transferred

7 (CHK_256): 256 data transferred
DCSIZE

Destination Chunk Transfer Size

0 (CHK_1): 1 data transferred

1 (CHK_4): 4 data transferred

2 (CHK_8): 8 data transferred

3 (CHK_16): 16 data transferred

4 (CHK_32): 32 data transferred

5 (CHK_64): 64 data transferred

6 (CHK_128): 128 data transferred

7 (CHK_256): 256 data transferred
SRC_WIDTH

Transfer Width for the Source

0 (BYTE): the transfer size is set to 8-bit width

1 (HALF_WORD): the transfer size is set to 16-bit width

2 (WORD): the transfer size is set to 32-bit width
DST_WIDTH

Transfer Width for the Destination

0 (BYTE): the transfer size is set to 8-bit width

1 (HALF_WORD): the transfer size is set to 16-bit width

2 (WORD): the transfer size is set to 32-bit width
DONE

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data