Atmel /AT91SAM9N12 /LCDC /LCDCFG0

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Interpret as LCDCFG0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLKPOL)CLKPOL 0 (CLKSEL)CLKSEL 0 (CLKPWMSEL)CLKPWMSEL 0 (CGDISBASE)CGDISBASE 0CLKDIV

Description

LCD Controller Configuration Register 0

Fields

CLKPOL

LCD Controller Clock Polarity

CLKSEL

LCD Controller Clock Source Selection

CLKPWMSEL

LCD Controller PWM Clock Source Selection

CGDISBASE

Clock Gating Disable Control for the Base Layer

CLKDIV

LCD Controller Clock Divider

Links

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