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Atmel /AT91SAM9N12 /LCDC /LCDCFG5

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Interpret as LCDCFG5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HSPOL)HSPOL 0 (VSPOL)VSPOL 0 (VSPDLYS)VSPDLYS 0 (VSPDLYE)VSPDLYE 0 (DISPPOL)DISPPOL 0 (DITHER)DITHER 0 (DISPDLY)DISPDLY 0 (OUTPUT_12BPP)MODE 0 (VSPSU)VSPSU 0 (VSPHO)VSPHO 0GUARDTIME

MODE=OUTPUT_12BPP

Description

LCD Controller Configuration Register 5

Fields

HSPOL

Horizontal Synchronization Pulse Polarity
VSPOL

Vertical Synchronization Pulse Polarity
VSPDLYS

Vertical Synchronization Pulse Start
VSPDLYE

Vertical Synchronization Pulse End
DISPPOL

Display Signal Polarity
DITHER

LCD Controller Dithering
DISPDLY

LCD Controller Display Power Signal Synchronization
MODE

LCD Controller Output Mode

0 (OUTPUT_12BPP): LCD output mode is set to 12 bits per pixel

1 (OUTPUT_16BPP): LCD output mode is set to 16 bits per pixel

2 (OUTPUT_18BPP): LCD output mode is set to 18 bits per pixel

3 (OUTPUT_24BPP): LCD output mode is set to 24 bits per pixel
VSPSU

LCD Controller Vertical Synchronization Pulse Setup Configuration
VSPHO

LCD Controller Vertical Synchronization Pulse Hold Configuration
GUARDTIME

LCD DISPLAY Guard Time

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data