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Atmel /AT91SAM9N12 /UDP /CSR0_ISOENDPT

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Interpret as CSR0_ISOENDPT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXCOMP)TXCOMP 0 (RX_DATA_BK0)RX_DATA_BK0 0 (RXSETUP)RXSETUP 0 (ISOERROR)ISOERROR 0 (TXPKTRDY)TXPKTRDY 0 (FORCESTALL)FORCESTALL 0 (RX_DATA_BK1)RX_DATA_BK1 0 (DIR)DIR 0 (CTRL)EPTYPE 0 (DTGLE)DTGLE 0 (EPEDS)EPEDS 0RXBYTECNT

EPTYPE=CTRL

Description

Endpoint Control and Status Register

Fields

TXCOMP

Generates an IN Packet with Data Previously Written in the DPR
RX_DATA_BK0

Receive Data Bank 0
RXSETUP

Received Setup
ISOERROR

A CRC error has been detected in an isochronous transfer
TXPKTRDY

Transmit Packet Ready
FORCESTALL

Force Stall (used by Control, Bulk and Isochronous Endpoints)
RX_DATA_BK1

Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
DIR

Transfer Direction (only available for control endpoints)
EPTYPE

Endpoint Type

0 (CTRL): Control

1 (ISO_OUT): Isochronous OUT

2 (BULK_OUT): Bulk OUT

3 (INT_OUT): Interrupt OUT

5 (ISO_IN): Isochronous IN

6 (BULK_IN): Bulk IN

7 (INT_IN): Interrupt IN
DTGLE

Data Toggle
EPEDS

Endpoint Enable Disable
RXBYTECNT

Number of Bytes Available in the FIFO

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data