Regviz

Atmel /AT91SAM9X25 /EMAC0 /TSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TSR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Atmel/AT91SAM9G20/EMAC/TSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UBR)UBR 0 (COL)COL 0 (RLES)RLES 0 (TGO)TGO 0 (BEX)BEX 0 (COMP)COMP 0 (UND)UND

Description

Transmit Status Register

Fields

UBR

Used Bit Read
COL

Collision Occurred
RLES

Retry Limit exceeded
TGO

Transmit Go
BEX

Buffers exhausted mid frame
COMP

Transmit Complete
UND

Transmit Underrun

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data