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Atmel /ATSAM3N4B /PWM /CMR0

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Interpret as CMR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MCK)CPRE0 (CALG)CALG 0 (CPOL)CPOL 0 (CPD)CPD

CPRE=MCK

Description

PWM Channel Mode Register (ch_num = 0)

Fields

CPRE

Channel Pre-scaler

0 (MCK): Master Clock

1 (MCKDIV2): Master Clock divided by 2

2 (MCKDIV4): Master Clock divided by 4

3 (MCKDIV8): Master Clock divided by 8

4 (MCKDIV16): Master Clock divided by 16

5 (MCKDIV32): Master Clock divided by 32

6 (MCKDIV64): Master Clock divided by 64

7 (MCKDIV128): Master Clock divided by 128

8 (MCKDIV256): Master Clock divided by 256

9 (MCKDIV512): Master Clock divided by 512

10 (MCKDIV1024): Master Clock divided by 1024

11 (CLKA): Clock A

12 (CLKB): Clock B
CALG

Channel Alignment
CPOL

Channel Polarity
CPD

Channel Update Period

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data