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Atmel /ATSAM3S1B /SUPC /SMMR

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Interpret as SMMR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SMTH0 (SMD)SMSMPL 0 (NOT_ENABLE)SMRSTEN 0 (NOT_ENABLE)SMIEN

SMSMPL=SMD, SMIEN=NOT_ENABLE, SMRSTEN=NOT_ENABLE

Description

Supply Controller Supply Monitor Mode Register

Fields

SMTH

Supply Monitor Threshold
SMSMPL

Supply Monitor Sampling Period

0 (SMD): Supply Monitor disabled

1 (CSM): Continuous Supply Monitor

2 (32SLCK): Supply Monitor enabled one SLCK period every 32 SLCK periods

3 (256SLCK): Supply Monitor enabled one SLCK period every 256 SLCK periods

4 (2048SLCK): Supply Monitor enabled one SLCK period every 2,048 SLCK periods
SMRSTEN

Supply Monitor Reset Enable

0 (NOT_ENABLE): the core reset signal “vddcore_nreset” is not affected when a supply monitor detection occurs.

1 (ENABLE): the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
SMIEN

Supply Monitor Interrupt Enable

0 (NOT_ENABLE): the SUPC interrupt signal is not affected when a supply monitor detection occurs.

1 (ENABLE): the SUPC interrupt signal is asserted when a supply monitor detection occurs.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data