Atmel /ATSAM3S1C /TWI0 /SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXCOMP)TXCOMP 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (SVREAD)SVREAD 0 (SVACC)SVACC 0 (GACC)GACC 0 (OVRE)OVRE 0 (NACK)NACK 0 (ARBLST)ARBLST 0 (SCLWS)SCLWS 0 (EOSACC)EOSACC 0 (ENDRX)ENDRX 0 (ENDTX)ENDTX 0 (RXBUFF)RXBUFF 0 (TXBUFE)TXBUFE

Description

Status Register

Fields

TXCOMP

Transmission Completed (automatically set / reset)

RXRDY

Receive Holding Register Ready (automatically set / reset)

TXRDY

Transmit Holding Register Ready (automatically set / reset)

SVREAD

Slave Read (automatically set / reset)

SVACC

Slave Access (automatically set / reset)

GACC

General Call Access (clear on read)

OVRE

Overrun Error (clear on read)

NACK

Not Acknowledged (clear on read)

ARBLST

Arbitration Lost (clear on read)

SCLWS

Clock Wait State (automatically set / reset)

EOSACC

End Of Slave Access (clear on read)

ENDRX

End of RX buffer

ENDTX

End of TX buffer

RXBUFF

RX Buffer Full

TXBUFE

TX Buffer Empty

Links

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