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Atmel /ATSAM3S2B /TWI1 /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (START)START 0 (STOP)STOP 0 (MSEN)MSEN 0 (MSDIS)MSDIS 0 (SVEN)SVEN 0 (SVDIS)SVDIS 0 (QUICK)QUICK 0 (SWRST)SWRST

Description

Control Register

Fields

START

Send a START Condition
STOP

Send a STOP Condition
MSEN

TWI Master Mode Enabled
MSDIS

TWI Master Mode Disabled
SVEN

TWI Slave Mode Enabled
SVDIS

TWI Slave Mode Disabled
QUICK

SMBUS Quick Command
SWRST

Software Reset

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data