Regviz

Atmel /ATSAM3S4C /PWM /CLK

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLK

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Atmel/ATSAM3S1C/PWM/CLK#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIVA0PREA0DIVB0PREB

Description

PWM Clock Register

Fields

DIVA

CLKA, CLKB Divide Factor
PREA

CLKA, CLKB Source Clock Selection
DIVB

CLKA, CLKB Divide Factor
PREB

CLKA, CLKB Source Clock Selection

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data