Atmel /ATSAM3S8C /SUPC /WUMR

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Interpret as WUMR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NOT_ENABLE)SMEN 0 (NOT_ENABLE)RTTEN 0 (NOT_ENABLE)RTCEN 0 (NOT_ENABLE)LPDBCEN0 0 (NOT_ENABLE)LPDBCEN1 0 (NOT_ENABLE)LPDBCCLR 0 (IMMEDIATE)WKUPDBC 0 (DISABLE)LPDBC

LPDBCEN0=NOT_ENABLE, LPDBCEN1=NOT_ENABLE, LPDBC=DISABLE, RTTEN=NOT_ENABLE, LPDBCCLR=NOT_ENABLE, WKUPDBC=IMMEDIATE, RTCEN=NOT_ENABLE, SMEN=NOT_ENABLE

Description

Supply Controller Wake Up Mode Register

Fields

SMEN

Supply Monitor Wake Up Enable

0 (NOT_ENABLE): the supply monitor detection has no wake up effect.

1 (ENABLE): the supply monitor detection forces the wake up of the core power supply.

RTTEN

Real Time Timer Wake Up Enable

0 (NOT_ENABLE): the RTT alarm signal has no wake up effect.

1 (ENABLE): the RTT alarm signal forces the wake up of the core power supply.

RTCEN

Real Time Clock Wake Up Enable

0 (NOT_ENABLE): the RTC alarm signal has no wake up effect.

1 (ENABLE): the RTC alarm signal forces the wake up of the core power supply.

LPDBCEN0

Low power Debouncer ENable WKUP0

0 (NOT_ENABLE): the WKUP0 input pin is not connected with low power debouncer.

1 (ENABLE): the WKUP0 input pin is connected with low power debouncer and can force a core wake up.

LPDBCEN1

Low power Debouncer ENable WKUP1

0 (NOT_ENABLE): the WKUP1input pin is not connected with low power debouncer.

1 (ENABLE): the WKUP1 input pin is connected with low power debouncer and can force a core wake up.

LPDBCCLR

Low power Debouncer Clear

0 (NOT_ENABLE): a low power debounce event does not create an immediate clear on first half GPBR registers.

1 (ENABLE): a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers.

WKUPDBC

Wake Up Inputs Debouncer Period

0 (IMMEDIATE): Immediate, no debouncing, detected active at least on one Slow Clock edge.

1 (3_SCLK): WKUPx shall be in its active state for at least 3 SLCK periods

2 (32_SCLK): WKUPx shall be in its active state for at least 32 SLCK periods

3 (512_SCLK): WKUPx shall be in its active state for at least 512 SLCK periods

4 (4096_SCLK): WKUPx shall be in its active state for at least 4,096 SLCK periods

5 (32768_SCLK): WKUPx shall be in its active state for at least 32,768 SLCK periods

LPDBC

Low Power DeBounCer Period

0 (DISABLE): Disable the low power debouncer.

1 (2_RTCOUT0): WKUP0/1 in its active state for at least 2 RTCOUT0 periods

2 (3_RTCOUT0): WKUP0/1 in its active state for at least 3 RTCOUT0 periods

3 (4_RTCOUT0): WKUP0/1 in its active state for at least 4 RTCOUT0 periods

4 (5_RTCOUT0): WKUP0/1 in its active state for at least 5 RTCOUT0 periods

5 (6_RTCOUT0): WKUP0/1 in its active state for at least 6 RTCOUT0 periods

6 (7_RTCOUT0): WKUP0/1 in its active state for at least 7 RTCOUT0 periods

7 (8_RTCOUT0): WKUP0/1 in its active state for at least 8 RTCOUT0 periods

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