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Atmel /ATSAM3U1C /SMC /TIMINGS0

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Interpret as TIMINGS0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TCLR0TADL0TAR0 (OCMS)OCMS 0TRR0TWB0RBNSEL 0 (NFSEL)NFSEL

Description

SMC Timings Register (CS_number = 0)

Fields

TCLR

CLE to REN Low Delay
TADL

ALE to Data Start
TAR

ALE to REN Low Delay
OCMS

Off Chip Memory Scrambling Enable
TRR

Ready to REN Low Delay
TWB

WEN High to REN to Busy
RBNSEL

Ready/Busy Line Selection
NFSEL

NAND Flash Selection

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data