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Atmel /ATSAM3U2C /DMAC /CHSR

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Interpret as CHSR

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https://regviz.com/r/Atmel/ATSAM3U2E/DMAC/CHSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENA0)ENA0 0 (ENA1)ENA1 0 (ENA2)ENA2 0 (ENA3)ENA3 0 (SUSP0)SUSP0 0 (SUSP1)SUSP1 0 (SUSP2)SUSP2 0 (SUSP3)SUSP3 0 (EMPT0)EMPT0 0 (EMPT1)EMPT1 0 (EMPT2)EMPT2 0 (EMPT3)EMPT3 0 (STAL0)STAL0 0 (STAL1)STAL1 0 (STAL2)STAL2 0 (STAL3)STAL3

Description

DMAC Channel Handler Status Register

Fields

ENA0

Enable [3:0]
ENA1

Enable [3:0]
ENA2

Enable [3:0]
ENA3

Enable [3:0]
SUSP0

Suspend [3:0]
SUSP1

Suspend [3:0]
SUSP2

Suspend [3:0]
SUSP3

Suspend [3:0]
EMPT0

Empty [3:0]
EMPT1

Empty [3:0]
EMPT2

Empty [3:0]
EMPT3

Empty [3:0]
STAL0

Stalled [3:0]
STAL1

Stalled [3:0]
STAL2

Stalled [3:0]
STAL3

Stalled [3:0]

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data