Regviz

Atmel /ATSAM3U2C /HSMCI /MR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Atmel/ATSAM3U2E/HSMCI/MR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIV0PWSDIV 0 (RDPROOF)RDPROOF 0 (WRPROOF)WRPROOF 0 (FBYTE)FBYTE 0 (PADV)PADV

Description

Mode Register

Fields

CLKDIV

Clock Divider
PWSDIV

Power Saving Divider
RDPROOF

Read Proof Enable
WRPROOF

Write Proof Enable
FBYTE

Force Byte Transfer
PADV

Padding Value

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data