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Atmel /ATSAM3U4C /ADC12B /IDR

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Interpret as IDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EOC0)EOC0 0 (EOC1)EOC1 0 (EOC2)EOC2 0 (EOC3)EOC3 0 (EOC4)EOC4 0 (EOC5)EOC5 0 (EOC6)EOC6 0 (EOC7)EOC7 0 (OVRE0)OVRE0 0 (OVRE1)OVRE1 0 (OVRE2)OVRE2 0 (OVRE3)OVRE3 0 (OVRE4)OVRE4 0 (OVRE5)OVRE5 0 (OVRE6)OVRE6 0 (OVRE7)OVRE7 0 (DRDY)DRDY 0 (GOVRE)GOVRE 0 (ENDRX)ENDRX 0 (RXBUFF)RXBUFF

Description

Interrupt Disable Register

Fields

EOC0

End of Conversion Interrupt Disable 0
EOC1

End of Conversion Interrupt Disable 1
EOC2

End of Conversion Interrupt Disable 2
EOC3

End of Conversion Interrupt Disable 3
EOC4

End of Conversion Interrupt Disable 4
EOC5

End of Conversion Interrupt Disable 5
EOC6

End of Conversion Interrupt Disable 6
EOC7

End of Conversion Interrupt Disable 7
OVRE0

Overrun Error Interrupt Disable 0
OVRE1

Overrun Error Interrupt Disable 1
OVRE2

Overrun Error Interrupt Disable 2
OVRE3

Overrun Error Interrupt Disable 3
OVRE4

Overrun Error Interrupt Disable 4
OVRE5

Overrun Error Interrupt Disable 5
OVRE6

Overrun Error Interrupt Disable 6
OVRE7

Overrun Error Interrupt Disable 7
DRDY

Data Ready Interrupt Disable
GOVRE

General Overrun Error Interrupt Disable
ENDRX

End of Receive Buffer Interrupt Disable
RXBUFF

Receive Buffer Full Interrupt Disable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data