LOCK_B=DISABLE, FIFOCFG=ALAP_CFG, LOCK_IF_L=CHUNK, SRC_H2SEL=SW, DST_H2SEL=SW, LOCK_IF=DISABLE, SOD=DISABLE
DMAC Channel Configuration Register (ch_num = 1)
| SRC_PER | Source with Peripheral identifier |
| DST_PER | Destination with Peripheral identifier |
| SRC_H2SEL | Software or Hardware Selection for the Source 0 (SW): Software handshaking interface is used to trigger a transfer request. 1 (HW): Hardware handshaking interface is used to trigger a transfer request. |
| DST_H2SEL | Software or Hardware Selection for the Destination 0 (SW): Software handshaking interface is used to trigger a transfer request. 1 (HW): Hardware handshaking interface is used to trigger a transfer request. |
| SOD | Stop On Done 0 (DISABLE): STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 (ENABLE): STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. |
| LOCK_IF | Interface Lock 0 (DISABLE): Interface Lock capability is disabled 1 (ENABLE): Interface Lock capability is enabled |
| LOCK_B | Bus Lock 0 (DISABLE): AHB Bus Locking capability is disabled. |
| LOCK_IF_L | Master Interface Arbiter Lock 0 (CHUNK): The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 (BUFFER): The Master Interface Arbiter is locked by the channel x for a buffer transfer. |
| AHB_PROT | AHB Protection |
| FIFOCFG | FIFO Configuration 0 (ALAP_CFG): The largest defined length AHB burst is performed on the destination AHB interface. 1 (HALF_CFG): When half FIFO size is available/filled, a source/destination request is serviced. 2 (ASAP_CFG): When there is enough space/data available to perform a single AHB access, then the request is serviced. |