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Atmel /ATSAM3X4C /PWM /CLK

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Interpret as CLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIVA0PREA0DIVB0PREB

Description

PWM Clock Register

Fields

DIVA

CLKA, CLKB Divide Factor
PREA

CLKA, CLKB Source Clock Selection
DIVB

CLKA, CLKB Divide Factor
PREB

CLKA, CLKB Source Clock Selection

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data