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Atmel /ATSAM3X4E /PMC /PMC_SCDR

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Interpret as PMC_SCDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UOTGCLK)UOTGCLK 0 (PCK0)PCK0 0 (PCK1)PCK1 0 (PCK2)PCK2

Description

System Clock Disable Register

Fields

UOTGCLK

Disable USB OTG Clock (48 MHz, USB_48M) for UTMI
PCK0

Programmable Clock 0 Output Disable
PCK1

Programmable Clock 1 Output Disable
PCK2

Programmable Clock 2 Output Disable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data