CPRE=MCK
PWM Channel Mode Register (ch_num = 5)
| CPRE | Channel Pre-scaler 0 (MCK): Master clock 1 (MCK_DIV_2): Master clock/2 2 (MCK_DIV_4): Master clock/4 3 (MCK_DIV_8): Master clock/8 4 (MCK_DIV_16): Master clock/16 5 (MCK_DIV_32): Master clock/32 6 (MCK_DIV_64): Master clock/64 7 (MCK_DIV_128): Master clock/128 8 (MCK_DIV_256): Master clock/256 9 (MCK_DIV_512): Master clock/512 10 (MCK_DIV_1024): Master clock/1024 11 (CLKA): Clock A 12 (CLKB): Clock B |
| CALG | Channel Alignment |
| CPOL | Channel Polarity |
| CES | Counter Event Selection |
| DTE | Dead-Time Generator Enable |
| DTHI | Dead-Time PWMHx Output Inverted |
| DTLI | Dead-Time PWMLx Output Inverted |